Freescale Semiconductor MCF5480 - Manual (Page 469)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 18-21
18.7.5 SDRAM Configuration Register 1 (SDCFG1)
The 32-bit read/write SDRAM configuration register 1 (SDCFG1) stores delay values necessary between
specific SDRAM commands. During initialization, software loads values to the register according to the
selected SDCLK frequency and SDRAM specifications. This register is reset only by a power-up reset
signal.
The read and write latency fields govern the relative timing of commands and data, and must be exact
values. All other fields govern the relative timing from one command to another, they have minimum
values but any larger value is also legal (but with decreased performance).
22 DRIVE Drive rule selection.
0 Tri-state except to write. SDDATA and SDDQS are only driven when necessary to perform a
write.
1 Drive except to read. SDDATA and SDDQS are only tristated when necessary to perform a
read. When not being driven for a write cycle, SDDATA hold the most recent value and SDDQS
are driven low.
This mode is intended for minimal applications only, to prevent floating signals and allow
unterminated board traces. However, terminated wiring is always recommended over
unterminated.
21–16 RCNT Refresh Count. Controls automatic refresh frequency. The number of bus clocks between refresh
cycles is (RC + 1) x 64.
RCNT = (t
REFI
/ (SDCLK x 64)) - 1, rounded down to the next integer value.
15–12 — Reserved. Should be cleared.
11–8 DQS_OE DQS output enable. Each DQS_OE bit is a master enable for the corresponding SDDQSn signal.
1 SDDQSn can drive as necessary, depending on commands and SDCR[DRIVE] setting.
0 SDDQSn can never drive. Use this value in SDR mode or in DDR mode with a “single DQS”
memory. Some 32-bit DDR devices only have a single DQS pin. Enable one of the SDDQSn
signals and disable the other three. Then short all 4 pins external to the part.
7–5 — Reserved. Should be cleared.
4 BUFF Buffering mode. Selects between buffered and unbuffered memory timing. Buffered and
unbuffered memory cannot be mixed.
1 System uses “buffered” memory modules.
0 System does not use “buffered” memory modules.
3 — Reserved. Should be cleared.
2 IREF Initiate Refresh (REF) command. Used to force a software initiated Refresh command.
1 Generate a Refresh command. All SDCSn signals are asserted simultaneously.
SDCR[CLK_EN] must be set before attempting to generate a software refresh command.
0 Do not generate a Refresh command.
1 IPALL Initiate Precharge All command. Used to force a software initiated PALL command.
1 Generate a PALL command. All SDCSn signals are asserted simultaneously. SDCR[CKE] must
be set before attempting to generate a software PALL command.
0 Do not generate a PALL command.
0 — Reserved. Should be cleared.
Table 18-11. SDCR Field Descriptions (Continued)
Bits Name Description