Freescale Semiconductor MCF5480 User Manual
Page 499
Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
19-15
19.3.2.2
Target Base Address Translation Register 0 (PCITBATR0)
13
PEE
Parity error interrupt enable. This bit enables CPU Interrupt generation when the PCI Parity Error
signal, PCIPERR, is sampled asserted. When enabled and PCIPERR asserts, software must
clear the PE status bit to clear the interrupt condition.
12
SEE
System error interrupt enable. This bit enables CPU Interrupt generation when a PCI system error
is detected on the PCISERR line. When enabled and PCISERR asserts, software must clear the
SE status bit to clear the interrupt condition.
11–1
—
Reserved, should be cleared.
0
PR
PCI reset. This bit controls the external PCIRESET. When this bit is cleared, the external
PCIRESET deasserts. Setting this bit does not reset the internal PCI controller. The application
software must not initiate PCI transactions while this bit is set. It is recommended that this bit be
programmed last during initialization.
The reset value of the bit is 1 (PCIRESET asserted).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
Base Address Translation 0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EN
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0xB64
Figure 19-10. Target Base Address Translation Register 0 (PCITBATR0)
Table 19-11. PCITBATR0 Field Descriptions
Bits
Name
Description
31–18
Base
Address
Translation 0
This base address register corresponds to a hit on the BAR0 in MCF548x PCI Type 0 Configuration
space register from PCI space. When there is a hit on MCF548x PCI BAR0 (MCF548x as Target),
the upper 14 bits of the address (256-Kbyte boundary) are written over by this register value to
address some space in MCF548x. In normal operation, this value should be written during the
initialization sequence only.
17–1
—
Reserved, should be cleared.
0
Enable 0
This bit enables a transaction in BAR0 space. If this bit is zero and a hit on MCF548 PCIBAR0
occurs, the target interface gasket will abort the PCI transaction.
Table 19-10.
PCIGSCR Field Descriptions (Continued)
Bits
Name
Description