Freescale Semiconductor MCF5480 User Manual
Page 501
Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
19-17
19.3.2.5
Initiator Window 0 Base/Translation Address Register (PCIIW0BTAR)
Table 19-13. PCITCR Field Descriptions
Bits
Name
Description
31–25
—
Reserved, should be cleared.
24
LD
Latency rule disable. This control bit applies only when MCF548 is Target. When set, it prevents the
PCI Controller from automatically issuing a retry disconnect due to the PCI 16/8 clock rule.
This bit should only be set when the XL<->PCI path is not in use. The only transactions that are retried
on the XL bus by the PCI are reads. Writes are held on the XL bus until either all data is posted (PCI
memory writes) and the XL bus data tenure is normally terminated or, in the case of I/O writes to PCI,
access is granted to the PCI bus and the connected write completes. When the LD bit is set, there is
never a timeout on the PCI bus because the PCI 16/8 clock rule is not obeyed. If there is inbound PCI
traffic (PCI->MCF548) and an XL bus write is held open by the PCI Controller, the PCI traffic will not
be granted access to XL bus. This is true for reads that have not been prefetched and when the
inbound write buffer is full. Both buses hang. Normal operation relies on the LD bit being cleared.
If used, the bit must be set before the 15th PCI clock for the first transfer and before the 7th clock for
other transfers.
23–17
—
Reserved, should be cleared.
16
P
Prefetch reads. This bit controls fetching a line from memory in anticipation of a request from the
external master. The target interface will continue to prefetch lines from memory as long as
PCIFRAME is asserted and there is space to store the data in the target read buffer.
Note: This bit only applies to PCI reads in the address range for BAR 1 (prefetchable memory).
Note: Prefetching is performed in response to a PCI memory-read-multiple command even if this bit
is cleared.
15–0
—
Reserved, should be cleared.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
Window 0 Base Address
Window 0 Address Mask
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
Window 0 Translation Address
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0xB70
Figure 19-13. Initiator Window 0 Base/Translation Address Register (PCIIW0BTAR)