10 initiator status register (pciisr), Initiator status register (pciisr) -21 – Freescale Semiconductor MCF5480 User Manual
Page 505
Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
19-21
19.3.2.10 Initiator Status Register (PCIISR)
Table 19-16. PCIICR Field Descriptions
Bits
Name
Description
31–27
—
Reserved, should be cleared.
26
REE
Retry error enable. This bit enables CPU Interrupt generation in the case of Retry Error termination
of a transaction. It may be desirable to mask CPU interrupts, but in such a case, software should
poll the status bits to prevent a possible lock-up condition.
25
IAE
Initiator abort enable. This bit enables CPU Interrupt generation in the case of Initiator Abort
termination of a transaction. It may be desirable to mask CPU interrupts, but in such a case,
software should poll the status bits to prevent a possible lock-up condition.
24
TAE
Target abort enable. This bit enables CPU Interrupt generation in the case of Target Abort
termination of a transaction. It may be desirable to mask CPU interrupts, but in such a case,
software should poll the status bits to prevent a possible lock-up condition.
23–8
—
Reserved, should be cleared.
7–0
Maximum
Retries
This bit field controls the maximum number of automatic PCI retries or master latency time-outs to
permit per write transaction. The retry counter is reset at the beginning of each write transaction
(i.e. it is not cumulative). Setting the Maximum Retries to 0x00 allows infinite automatic retry cycles
and latency time-outs before the write transaction will abort and, if open, send back an error on XL
bus. A slow or malfunctioning Target might issue infinite retry disconnects or hold the data tenure
open indefinitely, and therefore, permanently tie up the PCI bus if no Target Abort occurs.
The Maximum Retries register does not apply to reads because reads are always ARTRY’d on XL
bus when retry-terminated by the PCI target. This is done to avoid livelock scenarios where the
device we are requesting read data from needs to flush itself of posted writes going to MCF548
before it can return the read data. The incoming writes cannot be blocked in this case.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
RE
IA
TA
0
0
0
0
0
0
0
0
W
rwc
1
rwc
1
rwc
1
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0xB88
1
Bits 26-24 are read-write-clear (rwc).
—Hardware can set rwc bits, but cannot clear them.
—Software can clear rwc bits that are currently set by writing a 1 to the bit location. Writing a 1 to a rwc bit that is
currently a 0 or writing a 0 to any rwc bit has no effect.
Figure 19-18. Initiator Status Register (PCIISR)