3 tx transaction control register (pcittcr) – Freescale Semiconductor MCF5480 User Manual
Page 509
Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
19-25
19.3.3.1.3
Tx Transaction Control Register (PCITTCR)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
PCI_cmd
Max_Retries
W
Reset
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
Max_Beats
0
0
0
W
0
0
0
DI
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x8408
Figure 19-22. Tx Transaction Control Register (PCITTCR)
Table 19-21. PCITTCR Field Descriptions
Bits
Name
Description
31–28
—
Reserved, should be cleared.
27–24
PCI_cmd
The user writes this field with the desired PCI command to present during the address phase of
each PCI transaction. The default is Memory Write. This field is not checked for consistency and
if written to an illegal value, unpredictable results will occur. If not using the default value, the user
should write this register only once prior to any packet Restart.
23–16
Max_Retries The user writes this field with the maximum number of retries to permit “per packet”. The retry
counter is reset when the packet completes normally or is terminated by a master abort, target
abort, or an abort due to exceeding the retry limit. A slow or malfunctioning Target might issue
infinite disconnects and therefore permanently tie up the PCI bus. A finite (0x01 to 0xf)
Max_Retries value will detect this condition and generate an interrupt. Setting Max_Retries to
0x00 will not generate an interrupt but will permit re-arbitration of the PCI bus between each
disconnect.
15–11
—
Reserved, should be cleared.
10–8
Max_Beats
The user writes this register with the desired number of PCI data beats to attempt on each PCI
transaction. The default setting of 0 represents the maximum of eight beats per transaction. The
transmit controller will wait until sufficient bytes are in the Transmit FIFO to support the indicated
number of beats (NOTE: Each beat is four bytes). In the case that a packet is nearly complete and
less than the Max_Beats number of bytes remain to complete the packet, the Transmit Controller
will issue single-beat transactions automatically until the packet is finished.
7–5
—
Reserved, should be cleared.
4
W
Word transfer. The user writes this register to disable the two high byte enables of the PCI bus
during write transactions initiated by this interface. The default setting is 0, enable all 4 byte
enables.
3–1
—
Reserved, should be cleared.
0
DI
Disable address incrementing. The user writes this register to disable PCI address incrementing
between transactions. The default setting is 0, increment address by 4 (4 byte data bus).