5 tx next address register (pcitnar) – Freescale Semiconductor MCF5480 User Manual
Page 511
Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
19-27
19.3.3.1.5
Tx Next Address Register (PCITNAR)
21
FEE
FIFO error enable. User writes this bit high to enable CPU Interrupt generation in the case of FIFO
error termination of a packet transmission. It may be desirable to mask CPU interrupts in the case
that multichannel DMA is controlling operation, but in such a case software should poll the status
bits to prevent a possible lock-up condition.
20
SE
System error enable. User writes this bit high to enable CPU Interrupt generation in the case of
system error termination of a packet transmission.. It may be desirable to mask CPU interrupts in
the case that multichannel DMA is controlling operation, but in such a case software should be
polling the status bits to prevent a possible lock-up condition.
19
RE
Retry abort enable. User writes this bit high to enable CPU Interrupt generation in the case of retry
abort termination of a packet transmission. It may be desirable to mask CPU interrupts in the case
that multichannel DMA is controlling operation, but in such a case software should poll the status
bits to prevent a possible lock-up condition.
18
TAE
Target abort enable. User writes this bit high to enable CPU Interrupt generation in the case of
target abort termination of a packet transmission. It may be desirable to mask CPU interrupts in
the case that multichannel DMA is controlling operation, but in such a case software should poll
the status bits to prevent a possible lock-up condition.
17
IAE
Initiator abort enable. User writes this bit high to enable CPU Interrupt generation in the case of
initiator abort termination of a packet transmission. It may be desirable to mask CPU interrupts in
the case that multichannel DMA is controlling operation, but in such a case software should poll
the status bits to prevent a possible lock-up condition.
16
NE
Normal termination enable. User writes this bit high to enable CPU Interrupt generation at the
conclusion of a normally terminated packet transmission. This may or may not be desirable
depending on the nature of program control by multichannel DMA or the processor core.
15–0
—
Reserved, should be cleared.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
Next_Address
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
Next_Address
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x8410
Figure 19-24. Tx Next Address Register (PCITNAR)
Table 19-22. PCITER Field Descriptions (Continued)
Bits
Name
Description