8 tx status register (pcitsr) – Freescale Semiconductor MCF5480 User Manual
Page 513
Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
19-29
19.3.3.1.8
Tx Status Register (PCITSR)
Table 19-25. PCITDCR Field Descriptions
Bits
Name
Description
31–16
Bytes_Done
This status register indicates the number of bytes transmitted since the start of a packet. It is
updated at the end of each successful PCI data beat. For normally terminated packets the
Bytes_Done value and the Packet_Size values will be equal. If Continuous Mode is active, the
Bytes_Done value operates the same way. When the restart occurs for a continuous packet,
however, Bytes_Done will read 0 and the Packets_Done field will increment.
15–0
Packets_Done This status register indicates the number of previous packets transmitted and is active only if
continuous mode is in effect. The counter is reset if the following occurs:
• Reset Controller bit, PCITER[RC], is asserted (normal way to restart continuous mode)
• Master Enable bit, PCITER[ME], is negated during the current PCI data transmission and left
negated until the NT status bit asserts
The Master Enable bit, if negated as described, resets the Packets_Done status without
disturbing continuous mode addressing..
At any point in time, the total number of Bytes transmitted can be calculated as:
assuming Packet_Size is the same for all restart sequences and the Packets_Done register has
not been cleared.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
0
0
NT
BE3
BE2
BE1
FE
SE
RE
TA
IA
W
rwc
1
rwc
1
rwc
1
rwc
1
rwc
1
rwc
1
rwc
1
rwc
1
rwc
1
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x841C
1
Bits 24-16 are read-write-clear (rwc).
—Hardware can set rwc bits, but cannot clear them.
—Software can clear rwc bits that are currently set by writing a 1 to the bit location. Writing a 1 to a rwc bit that is
currently a 0 or writing a 0 to any rwc bit has no effect.
Figure 19-27. Tx Status Register (PCITSR)
Table 19-26. PCITSR Field Descriptions
Bits
Name
Description
31–25
—
Reserved, should be cleared.
24
NT
Normal termination. This bit is set when any packet terminates normally. It is not set for abnormally
terminated packets. An interrupt will be generated by this condition if the PCITER[NE] bit is set.
This bit is cleared by writing ‘1’ to it.
Packets_Done
Packet_Size
×
(
) Bytes_Done
+