11 tx fifo control register (pcitfcr) – Freescale Semiconductor MCF5480 User Manual
Page 516
MCF548x Reference Manual, Rev. 3
19-32
Freescale Semiconductor
19.3.3.1.11 Tx FIFO Control Register (PCITFCR)
Table 19-28. PCITFSR Field Descriptions
Bits
Name
Description
31
IP
Illegal Pointer. An address outside the FIFO controller’s memory range has been written to one of
the user visible pointers. This bit will cause the FIFO error output to assert unless the IP_MASK bit
in the FIFO Controller register is set. Resetting the FIFO will clear this condition and the bit is
cleared by writing a one to it.
30
TXW
Transmit Wait Condition. Since the Transmit Controller waits for enough data in the FIFO to satisfy
each PCI transaction before the transfer initiates, this bit will not assert.
29–24
—
Reserved, should be cleared.
23
FAE
Frame accept error. This module does not support data framing functionality, so this bit should be
ignored.
22
RXW
Receive wait condition. Since this FIFO is configured as a Transmit FIFO (i.e. the PCI controller
only reads from this FIFO), this bit will not assert.
21
UF
Underflow. This bit indicates that the read pointer has surpassed the write pointer. In other words
the FIFO has been read beyond Empty. Resetting the FIFO will clear this condition and the bit is
cleared by writing a one to it.
20
OF
Overflow. This bit indicates that the write pointer has surpassed the read pointer. In other words
the FIFO has been written beyond Full. Resetting the FIFO will clear this condition and the bit is
cleared by writing a one to it.
19
FR
Frame ready. The FIFO has a complete Frame of data ready for transmission. This module does
not provide support for data framing functionality, so this bit should be ignored.
18
Full
The FIFO is Full. This is not a sticky bit or error condition. The Full indication tracks with the state
of the FIFO.
17
Alarm
The FIFO is at or above the Alarm “watermark”, as set by the user according to the Alarm and
Control registers settings. This is not a sticky bit or error indication.
16
Empty
The FIFO is empty. This is not a sticky bit or error condition.
15–0
—
Reserved, should be cleared.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
WFR
0
0
GR
IP_
MASK
FAE_
MASK
RXW_
MASK
UF_
MASK
OF_
MASK
TXW_
MASK
0
0
W
Reset
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x8448
Figure 19-30. Tx FIFO Control Register (PCITFCR)