13 tx fifo read pointer register (pcitfrpr) – Freescale Semiconductor MCF5480 User Manual
Page 518
MCF548x Reference Manual, Rev. 3
19-34
Freescale Semiconductor
19.3.3.1.13 Tx FIFO Read Pointer Register (PCITFRPR)
Table 19-30. PCITFAR Field Descriptions
Bits
Name
Description
31–12
—
Reserved, should be cleared.
11–7
Alarm
Bits 11-7 are hardwired low.
6–0
Bits 6-0 are programmable to control a 128-byte FIFO. User writes these bits to set low level
“watermark”, which is the point where FIFO asserts request for multichannel DMA controller data
filling. Value is in bytes. For example, with Alarm = 32 (0x20), an alarm condition occurs when the
FIFO contains less than 32bytes. Once asserted, alarm does not negate until high level mark is
reached, as specified by FIFO control register granularity (GR[2:0]) bits.
Note: The Alarm setting should be programmed to a value greater than or equal to Max_Beats * 4
or else data transfer may stall. The Tx controller waits for enough data to form a burst of Max_Beats
to be in the FIFO before it will transmit data. For a Max_Beats value of 0(8 beats), Alarm should be
programmed to 32 or greater.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
ReadPtr
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x8450
Figure 19-32. Tx FIFO Read Pointer Register (PCITFRPR)
Table 19-31. PCITFRPR Field Descriptions
Bits
Name
Description
31–7
—
Reserved, should be cleared.
6–0
ReadPtr
This value is maintained by FIFO hardware and is not normally written by the user. It can be adjusted
in special cases, but this disrupts data flow integrity. The value represents the Read address
presented to the FIFO RAM.