3 rx transaction control register (pcirtcr) – Freescale Semiconductor MCF5480 User Manual
Page 521
Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
19-37
19.3.3.2.3
Rx Transaction Control Register (PCIRTCR)
Table 19-34. PCIRSAR Field Descriptions
Bits
Name
Description
31–0
Start_Add
The user writes this register with the desired starting address for the current packet. This is the
address which will be first presented on the external PCI bus and then auto-incremented as
necessary. Addressing is assumed to be sequential from the start address unless the PCIRTCR[DI]
bit is set. This register will not increment as the PCI packet proceeds.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
PCI_cmd
Max_Retries
W
Reset
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
FB
0
Max_Beats
0
0
0
W
0
0
0
DI
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x8488
Figure 19-36. Rx Transaction Control Register (PCIRTCR)
Table 19-35. PCIRTCR Field Descriptions
Bits
Name
Description
31–28
—
Reserved, should be cleared.
27–24
PCI_cmd
The user writes this field with the desired PCI command to present during the address phase of
each PCI transaction. The default is Memory Read Multiple. This field is not checked for consis-
tency and if written to an illegal value, unpredictable results will occur. If not using the default
value, the user should write this register only once prior to any packet Restart.
23–16
Max_Retries The user writes this field with the maximum number of retries to permit “per packet”. The retry
counter is reset when the packet completes normally or is terminated by a master abort, target
abort, or an abort due to exceeding the retry limit. A slow or malfunctioning Target might issue infi-
nite disconnects and therefore permanently tie up the PCI bus. A finite (0x01 to 0xf) Max_Retries
value will detect this condition and generate an interrupt. Setting Max_Retries to 0x00 will not
generate an interrupt but will permit re-arbitration of the PCI bus between each disconnect.
15–13
—
Reserved, should be cleared.