4 rx enables register (pcirer) – Freescale Semiconductor MCF5480 User Manual
Page 522
MCF548x Reference Manual, Rev. 3
19-38
Freescale Semiconductor
19.3.3.2.4
Rx Enables Register (PCIRER)
12
FB
Full burst. This is the full burst bit and it supersedes the Max_Beats setting. Since Max_Beats
provides support for up to 8-beat bursts, the Full burst bit should not be set for packets sizes of
8-beats or less. In Full burst mode, the user must program Packets_Size to at least 40 bytes.
If full burst is set, no check of the Receive FIFO fullness is done and the PCI transaction is
immediately started when Packet_Size register is written and the Rx controller gains the PCI bus.
The PCI transaction will continue with multiple data beats until the full packet is transferred (up to
65,532 bytes). The full burst operation will not relinquish the PCI bus to any other internal PCI
initiator, Tx controller or the XL bus initiator, until all packet bytes are received.
All FIFO checks Rx Controller are disabled in this mode. It is up to the Multi-Channel DMA to keep
the Rx FIFO from being overrun by the continuous incoming PCI burst data.
11
Reserved
Reserved, should be cleared.
10–8
Max_Beats
The user writes this register with the desired number of PCI data beats to attempt on each PCI
transaction. The default setting of 0 represents the maximum of eight beats per transaction. The
receive controller will wait until sufficient space is in the Receive FIFO to support the indicated
number of beats (Note: Each beat is four bytes). In the case that a packet is nearly complete and
less than the Max_Beats number of bytes remain to complete the packet, the Receive Controller
will issue single-beat transactions automatically until the packet is finished.
7–5
—
Reserved, should be cleared.
4
W
The user writes this register to disable the two high byte enables of the PCI bus during scpci
initiated read transactions. The default setting is 0, enable all 4 byte enables.
3–1
—
Reserved, should be cleared.
0
DI
The user writes this register to disable PCI address incrementing between transactions. The
default setting is 0, increment address by 4 (4 byte data bus).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
RC
RF
FE
CM
BE
0
0
ME
0
0
FEE
SE
RE
TAE
IAE
NE
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x848C
Figure 19-37. Rx Enables Register (PCIRER)
Table 19-35. PCIRTCR Field Descriptions (Continued)
Bits
Name
Description