5 rx next address register (pcirnar) – Freescale Semiconductor MCF5480 User Manual
Page 524
MCF548x Reference Manual, Rev. 3
19-40
Freescale Semiconductor
19.3.3.2.5
Rx Next Address Register (PCIRNAR)
17
IAE
Initiator abort enable. User writes this bit high to enable CPU Interrupt generation in the case of ini-
tiator abort error termination of a packet transmission. It may be desirable to mask CPU interrupts
in the case that Multi-Channel DMA is controlling operation, but in such a case software should poll
the status bits to prevent a possible lock-up condition.
16
NE
Normal termination enable. User writes this bit high to enable CPU Interrupt generation at the con-
clusion of a normally terminated packet transmission. This may or may not be desirable depending
on the nature of program control by Multi-Channel DMA or the processor core.
15–0
—
Reserved, should be cleared.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
Next_Address
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
Next_Address
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x8490
Figure 19-38. Rx Next Address Register (PCIRNAR)
Table 19-37. PCIRNAR Field Descriptions
Bits
Name
Description
31–0
Next_Address This status register contains the next (unread) PCI address and is updated at the successful
completion of each PCI data beat. It represents a byte address and is updated with a user-written
Start_Add value when Start_Add is reloaded. This register is intended to be accurate even if an
abnormal PCI bus termination occurs.
Table 19-36. PCIRER Field Descriptions (Continued)
Bits
Name
Description