Freescale Semiconductor MCF5480 - Manual (Page 546)

MCF548x Reference Manual, Rev. 3
19-62 Freescale Semiconductor
19.4.4.2.2 Type 1 Configuration Translation
For Type 1 translations, the 30 high-order bits of the configuration address register are copied without
modification onto the AD[31:2] signals during the address phase. The AD[1:0] signals are driven to 0b01
during the address phase to indicate a Type 1 configuration cycle.
19.4.4.3 Interrupt Acknowledge Transactions
When the MCF548x detects a read from an I/O defined window ( Section 19.3.2.8, “Initiator Window
Configuration Register (PCIIWCR)” ), it checks the enable flag, bus number, and the device number in the
configuration address register ( Section 19.3.2.11, “Configuration Address Register (PCICAR)” ). If the
enable bit is set, the bus number corresponds to the local PCI bus (bus number = 0x00), and the device
number is all 1’s (device number = 0b1_1111), then an interrupt acknowledge transaction is initiated. If
the bus number indicates a subordinate PCI bus (bus number != 0x00), a Type 1 configuration cycle is
initiated, similar to any other configuration cycle for which the bus number does not match. The function
number and Dword values are ignored.
The interrupt acknowledge command (0b0000) is driven on the PCICXBE[3:0] signals and the address bus
is driven with a stable pattern during the address phase, but a valid address is not driven. The address of
the target device during an interrupt acknowledge is implicit in the command type. Only the system
interrupt controller on the PCI bus should respond to the interrupt acknowledge and return the interrupt
vector on the data bus during the data phase. The size of the interrupt vector returned is indicated by the
value driven on the PCICXBE[3:0] signals.
19.4.4.4 Special Cycle Transactions
When the MCF548x detects a write to an I/O defined window ( Section 19.3.2.8, “Initiator Window
Configuration Register (PCIIWCR)” ), it checks the enable flag, bus number, and the device number in the
configuration address register ( Section 19.3.2.11, “Configuration Address Register (PCICAR)” ). If the
enable bit is set, the bus number corresponds to the local PCI bus (bus number = 0x00), and the device
number is all 1’s (device number = 0b1_1111), then a Special Cycle transaction is initiated. If the bus
number indicates a subordinate PCI bus (where the bus number field is not 0x00), a Type 1 configuration
cycle is initiated, similar to any other configuration cycle for which the bus number does not match. The
function number and Dword values are ignored.
The Special Cycle command (0b0001) is driven on the PCICXBE[3:0] signals and the address bus is
driven with a stable pattern during the address phase, but contains no valid address information. The
Special Cycle command contains no explicit destination address, but broadcast to all agents on the same
bus segment. Each receiving agent must determine whether the message is applicable to it. PCI agent will
never assert DEVSEL in response to a Special Cycle command. Master Abort is the normal termination
for a Special Cycle and no errors are reported for this case of Master Abort termination. This command is
basically a broadcast to all agents, and interested agents accept the command and process the request.
Note, Special Cycle commands do not cross PCI-to-PCI bridges. If a master wants to generate a Special
Cycle command on a specific bus in the hierarchy that is not its local bus, it must use a Type 1
configuration write command to do so. Type 1 configuration write commands can traverse PCI-to-PCI
bridges in both directions for the purpose of generating Special Cycle commands on any bus in the
hierarchy and are restricted to a single data phase in length. However, the master must know the specific
bus on which it desires to generate the Special Cycle command and cannot simply do a broadcast to one
bus and expect it to propagate to all buses.
During the data phase, PCIAD[31:0] contain the Special Cycle message and an optional data field. The
Special Cycle message is encoded on the 16 least significant bits (PCIAD[15:0]) and the optional data field
is encoded on the most significant bits (PCIAD[31:16]). The Special Cycle message encodings are