Freescale Semiconductor MCF5480 - Manual (Page 584)

MCF548x Reference Manual, Rev. 3
21-14 Freescale Semiconductor
21.3.2.5 FlexCAN Error Counter Register (ERRCNT)
This register has two 8-bit fields reflecting the value of two FlexCAN error counters: transmit error counter
(TXECTR) and receive error counter (RXECTR). The rules for increasing and decreasing these counters
are described in the CAN protocol and are completely implemented in the FlexCAN module. Both
counters are read-only except in freeze mode, where they can be written by the CPU.
Writing to the error counter register while in freeze mode is an indirect operation. The data is first written
to an auxiliary register and then an internal request/acknowledge procedure across clock domains is
executed. All this is transparent to the user, except for the fact that the data will take some time to be
actually written to the register. If desired, software can poll the register to discover when the data was
actually written.
FlexCAN responds to any bus state as described in the protocol, e.g. transmit error-active or error-passive
flag, delay its transmission start time (error-passive), and avoid any influence on the bus when in bus off
state. The following are the basic rules for FlexCAN bus state transitions:
• If the value of TXECTR or RXECTR increases to be greater than or equal to 128, the FLTCONF
field in the error and status register is updated to reflect error-passive state.
• If the FlexCAN state is error-passive, and either TXECTR or RXECTR decrements to a value less
than or equal to 127 while the other already satisfies this condition, the FLTCONF field in the error
and status register is updated to reflect error-active state.
• If the value of TXECTR increases to be greater than 255, the FLTCONF field in the error and status
register is updated to reflect bus off state, and an interrupt may be issued. The value of TXECTR
is then reset to zero.
• If FlexCAN is in bus off state, then TXECTR is cascaded together with another internal counter to
count the 128th occurrences of 11 consecutive recessive bits on the bus. Hence, TXECTR is reset
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 0 MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16
W
Reset 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MI15 MI14 MI13 MI12 MI11 MI10 MI9 MI8 MI7 MI6 MI5 MI4 MI3 MI2 MI1 MI0
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reg
Addr
MBAR + 0xA018 (RX15MASK0); 0xA818 (RX15MASK1)
Figure 21-9. FlexCAN Rx15 Mask Register (RX15MASK)
Table 21-7. RX15MASK Field Descriptions
Bits Name Description
31–29 — Reserved, should be cleared.
28–18 MI28–MI18 Standard ID mask bits. These bits are the same mask bits for the Standard and Extended
Formats.
17–0 MI17–MI0 Extended ID mask bits. These bits are used to mask comparison only in Extended Format.