Freescale Semiconductor MCF5480 - Manual (Page 587)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 21-17
21.3.2.7 Interrupt Mask Register (IMASK)
IMASK contains one interrupt mask bit per buffer. It enables the CPU to determine which buffer will
generate an interrupt after a successful transmission/reception (that is, when the corresponding IFLAG bit
is set).
The interrupt mask register contains two 8-bit fields: bits 15-8 (IMASK_H) and bits 7-0 (IMASK_L). The
register can be accessed by the master as a 16-bit register, or each byte can be accessed individually using
an 8-bit (byte) access cycle.
8 RXWRN Receiver error status flag. The RXWARN status flag reflects the status of the FlexCAN receive error
counter.
0 Receive error counter
< 96
1 RxErrCounter
≥ 96
7 IDLE Idle status. The IDLE bit indicates when there is activity on the CAN bus.
0 The CAN bus is not idle.
1 The CAN bus is idle.
6 TXRX Transmit/receive status. The TX/RX bit indicates when the FlexCAN module is transmitting or
receiving a message. TX/RX has no meaning when IDLE = 1.
0 The FlexCAN is receiving a message if IDLE = 0.
1 The FlexCAN is transmitting a message if IDLE = 0.
5–4 FLTCONF Fault confinement state. This 2-bit field indicates the confinement state of the FlexCAN module, as
shown below. If the LOM bit in the control register is asserted, the FLTCONF field will indicate
error-passive. Since the control register is not affected by soft reset, the FLTCONF field will not be
affected by soft reset if the LOM bit is asserted.
00 Error active
01 Error passive
1x Bus off
3 — Reserved, should be cleared.
2 BOFFINT Bus off interrupt. The BOFFINT bit is used to request an interrupt when the FlexCAN enters the bus
off state.
0 No bus off interrupt requested.
1 When the FlexCAN state changes to bus off, this bit is set, and if the BOFFMSK bit in CANCTRL
is set, an interrupt request is generated. This interrupt is not requested after reset.
1 ERRINT Error interrupt. The ERRINT bit is used to request an interrupt when the FlexCAN detects a transmit
or receive error.
0 No error interrupt request.
1 If an event which causes one of the error bits in the error and status register to be set occurs, the
error interrupt bit is set. If the ERRMSK bit in CANCTRL is set, an interrupt request is generated.
To clear this bit, first read it as a one, then write as a zero. Writing a one has no effect.
0 — Reserved, should be cleared.
Table 21-8. ERRSTAT Field Descriptions (Continued)
Bits Name Description