16 ptd debug registers, Ptd debug registers -19 – Freescale Semiconductor MCF5480 User Manual

Page 739

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Memory Map/Register Definitions

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor

24-19

24.3.3.16 PTD Debug Registers

The PTD Debug register allows access to internal read-only PTD status registers. A different internal status

register can be viewed by writing to the register. That register will stay selected until a different value is

written to this location (MBAR+0x8080), and the next time this address is read, the corresponding register

will be driven.

16

T

Triggered.This bit indicates that a DMA breakpoint has occurred with the current settings. Status bit
is sticky and requires a 1 to be written to it to clear it. The writing of a 0 to this bit has no effect. This
bit is set to 0 at reset.
0 Armed or normal operation
1 Triggered or debug mode

15–0

Task

Blocked

Task Blocked. Each bit corresponds to one of the 16 task numbers. The value of the register bit
reflects the debug state of the task number. A bit is cleared by writing a 1 to that bit location; writing
a 0 has no effect. At system reset, all bits are initialized to logic zero.
0 Unblocked or normal operation
1 Blocked, task has been blocked due to a breakpoint

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

R

PTDDBG[31:16]

W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R

PTDDBG[15:0]

W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Reg

Addr

MBAR + 0x8080

Figure 24-19. PTD Debug Register (PTDDBG)

Table 24-17. PTD Debug Register Descriptions

Value

Written

Reg Name

Description

0

Request

PTDDBG[31:0] reflects the current status of the 31 initiators described in the Initiator Mux
Control Register (IMCR).

1

regInitiator

PTDDBG[15:0] reflects whether the corresponding task is valid and the current initiator for
that task is asserted.

2

taskValid

PTDDBG[15:0] reflects the state of the V bit (initiator is valid) in each of the Task Control
Registers (TCRs).

3

hold

PTDDBG[15:0] reflects the state of the HLD bit in the priority registers for the
corresponding task.

Table 24-16. Debug Status Field Descriptions (Continued)

Bits

Name Description

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