Freescale Semiconductor MCF5480 - Manual (Page 757)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 25-5
25.2.2.2 Comm Timer Configuration Register (CTCRn)—Variable Timer Channel
This register provides programming options for each variable timer channel. These channels can also be
programmed as a baud clock generator or initiator.
Table 25-3. CTCRn—Fixed Timer Channel Field Descriptions
Bits Name Description
31 I Interrupt. This bit is set whenever the timerInterrupt signal asserts in the fixed timer. This indicates
that the cAcknowledge signal has arrived too far into the current cycle to be completed within that
period or that it was too short in duration to satisfy the request. Writing a 1 will clear the bit.
0 Indicates that no interrupt has occurred or is pending.
1 Indicates that an interrupt has occurred or is pending.
30–25 — Reserved, should be cleared.
24 IM Interrupt mask. Determines if the timer interrupt will be passed on to the interrupt controller.
0 The timer interrupt is not masked. When the I bit is set, the timer interrupt will be passed to the
interrupt controller.
1 The timer interrupt is masked. The I bit will be set, but no interrupt occurs.
23 M Mode. Selects between baud clock generator mode and task initiator mode. It is set to 1 at reset.
0 Baud clock generator. In this mode, the timer output is a free running clock. Following
initialization, both timer channels react in the same way.
1 Task initiator mode. In this mode, the timer output is a bandwidth controlled initiator request signal
for the multichannel DMA. The initiator output is dependent upon the cAcknowledge signal from
the DMA. In the fixed timer channels, the percent active time is only counted while the
cAcknowledge is asserted. In contrast, the variable timer channels will count the percent active
time from beginning to end upon the first assertion of the cAcknowledge.
22–20 PCT Percent active time select. Selects the percent of the period that the cInitiator signal is asserted after
the cAcknowledge signal is received. They are set to 101 at reset.
000 100
percent
001 50 percent
010 25 percent
011 12.5 percent
100 6.25 percent
101 OFF
110–111 Reserved
19–16 S Clock enable source select. Selects the clock rate for the fixed timer channels. The clock rate for the
timer is the internal system clock divided by an 8-bit prescaler.
0000 Sysclk/1
0001 Sysclk/2
0010 Sysclk/4
0011 Sysclk/8
0100 Sysclk/16
0101 Sysclk/32
0110 Sysclk/64
0111 Sysclk/128
1000 Sysclk/256
1001 External clock
15–0 CRV Counter reference value. These 16 bits define the period of the timer i.e.: 0004 written into these
bits signifies that the period is 4 timer clock cycles long. The counter reference value is set to
0xFFFF at reset.