Freescale Semiconductor MCF5480 - Manual (Page 780)

MCF548x Reference Manual, Rev. 3
26-18 Freescale Semiconductor
26.3.3.8 Auxiliary Control Register (PSCACRn)
PSCACR controls the handshake of the transmitter/receiver.
26.3.3.9 Interrupt Status Register (PSCISRn)
PSCISR provides status for all potential interrupt sources. The contents of these registers are masked by
the PSCIMR register. If a flag in the PSCISR is set and the corresponding bit in PSCIMR is also set, the
internal interrupt output is asserted. If the corresponding bit in the PSCIMR is cleared, the state of the bit
in the PSCISR has no effect on the output.
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0
W IEC0
Reset 0 0 0 0 0 0 0 0
Reg
Addr
MBAR + 0x8610 (PSC0); 0x8710 (PSC1); 0x8810 (PSC2); 0x8910 (PSC3)
Figure 26-13. Auxiliary Control Register (PSCACRn)
Table 26-12. PSCACRn Field Descriptions
Bits Name Description
7–1 — Reserved, should be cleared.
0 IEC0 Interrupt enable control for D_CTS.
0 D_CTS has no effect on the IPC in the PSCISR.
1 When the D_CTS becomes high, IPC bit in the PSCISR is set (and it will cause an interrupt if the
mask is not set).
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode
R IPC 0 0 0 0 0 RXRDY_FU TXRDY DEOF ERR 0 0 0 0 0 0 MIR /
FIR
W
R IPC 0 0 0 0 0 RXRDY_FU TXRDY 0 ERR 0 0 0 0 0 0
Modem
W
R IPC 0 0 0 0 DB RXRDY_FU TXRDY 0 ERR 0 0 0 0 0 0
UART
W
R IPC 0 0 0 0 DB RXRDY_FU TXRDY DEOF ERR 0 0 0 0 0 0
SIR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reg
Addr
MBAR + 0x8614 (PSC0); 0x8714 (PSC1); 0x8814 (PSC2); 0x8914 (PSC3)
Figure 26-14. Interrupt Status Register (PSCISRn)