Freescale Semiconductor MCF5480 - Manual (Page 781)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 26-19
26.3.3.10 Interrupt Mask Register (PSCIMRn)
The PSCIMR selects the corresponding bits in the PSCISR that cause an interrupt. If one of the bits in the
PSCISR is set and the corresponding bit in the PSCIMR is also set, the internal interrupt output is asserted.
If the corresponding bit in the PSCIMR is zero, the state of the bit in the PSCISR has no effect on the
interrupt output. The PSCIMR does not mask the reading of the PSCISR.
Table 26-13. PSCISRn Field Descriptions
Bits Name Descriptions
15 IPC Input port change. This bit is set when PSCIPCRn[D_CTS] and PSCACRn[IEC0] are set.
14–11 — Reserved, should be cleared.
10 DB In UART / SIR, this is a Delta break. The receiver detected the beginning or the end of a break
condition.
In other modes, this is reserved.
9 RXRDY Receive data is ready. (selected if PSCMR1[6] = 0)
0 There is no data in the RxFIFO.
1 There is at least one data in the RxFIFO.
FU RxFIFO over threshold. (selected if PSCMR1[6] = 1)
0 The number in the RxFIFO is less than the threshold.
1 There is more than or equal number of data in the RxFIFO.
8 TXRDY Transmitter ready
0 There are more than the threshold number of data in the TxFIFO or transmitter is not enabled.
1 The number of data in the TxFIFO is less than or equal to the threshold (as defined in PSCTFAR).
7 DEOF For modem and UART modes this bit is reserved.
For SIR and MIR modes, this bit signifies detect end of frame or the RxFIFO contains EOF (Copy of
DEOF in PSCSR)
6 ERR OR of all errors status including FIFO errors.
0 No error was detected.
1 At least one error occurred
5–0 — Reserved, should be cleared.