Freescale Semiconductor MCF5480 - Manual (Page 825)

Memory Map and Registers
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 27-7
27.6.2 DSPI Transfer Count Register (DTCR)
The DTCR contains a counter that indicates the number of SPI transfers made. The transfer counter is
intended to assist in queue management. The user must not write to the DTCR while the DSPI is in the
running state.
27.6.3 DSPI Clock and Transfer Attributes Registers 0–7 (DCTARn)
Each SPI transfer selects a DCTAR register from which it gets its transfer attributes. By combining these
attributes the transfer is configured. The user must not write to the DCTAR registers while the DSPI is in
the running state.
In master mode, the DCTAR registers define combinations of transfer attributes such as transfer size, clock
phase and polarity, data bit ordering, baud rate, and various delays. When the DSPI is thus configured as
7–1 — Reserved, should be cleared.
0 HALT Halt. Provides a mechanism for software to start and stop DSPI transfers. See Section 27.7.1,
“Start and Stop of DSPI Transfers ” for details on the operation of this bit.
0 Start transfers
1 Stop transfers on the next frame boundary
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R SPI_TCNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reg
Addr
MBAR + 0x8A08
Figure 27-3. DSPI Transfer Count Register (DTCR)
Table 27-4. DMCR Field Descriptions
Bits Name Description
31–16 SPI_TCNT SPI transfer counter. SPI_TCNT is used to keep track of the number of SPI transfers made. The
SPI_TCNT field counts the number of SPI transfers the DSPI makes. The SPI_TCNT field is
incremented every time the last bit of an SPI frame is transmitted. A value written to SPI_TCNT
presets the counter to that value. SPI_TCNT is reset to zero at the beginning of the frame when the
CTCNT field is set in the executing SPI command. The transfer counter ‘wraps around’ i.e.
incrementing the counter past 65535 resets the counter to zero.
15–0 — Reserved, should be cleared.
Table 27-3. DMCR Field Descriptions (Continued)
Bits Name Description