8 dspi tx fifo debug registers 0-3 (dtfdrn), 9 dspi rx fifo debug registers 0-3 (drfdrn), Dspi tx fifo debug registers 0–3 (dtfdrn) -17 – Freescale Semiconductor MCF5480 User Manual
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Memory Map and Registers
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
27-17
27.6.8
DSPI Tx FIFO Debug Registers 0–3 (DTFDRn)
The DTFDRn registers provide visibility into the Tx FIFO for debugging purposes. Each register is an
entry in the Tx FIFO. The registers are read-only and cannot be modified. Reading the DTFDRn registers
does not alter the state of the Tx FIFO
.
27.6.9
DSPI Rx FIFO Debug Registers 0–3 (DRFDRn)
The DRFDR0 – DRFDR3 registers provide visibility into the Rx FIFO for debugging purposes. Each
register is an entry in the Rx FIFO. The DRFDR registers are read-only. Reading the DRFDR_x registers
does not alter the state of the Rx FIFO.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
TXCMD
W
Reset
0000_0000_0000_0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
TXDATA
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x8A3C–8A48
Figure 27-9. DSPI Tx FIFO Debug Register (DTFDRn)
Table 27-12. DTFDRx Field Descriptions
Bits
Name
Description
31–16
TXCMD
Transmit command. The TXCMD field contains the command that sets the transfer
attributes for the SPI data. Commands include the following:
CONT Select a continuous chip format
CTAS Select clock and transfer attributes
EOQ Enable an end of queue bit for the transfer
CTCNT Clear the SPI transfer counter
CSn Select which DSPICS signal is asserted for the transfer in question
See
Section 27.6.6, “DSPI Tx FIFO Register (DTFR)
” for details on the command field.
15–0
TXDATA
Transmit data. The TXDATA field contains the SPI data to be shifted out.