Freescale Semiconductor MCF5480 - Manual (Page 861)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 28-7
28.3.2.5 I
2
C Data I/O Register (I2DR)
While in master-receive mode, reading the I2DR allows a read to occur and initiates the next data byte to
be received. In slave mode, the same function is available once the I
2
C has received its slave address.
28.3.2.6 I
2
C Interrupt Control Register (I2ICR)
The I
2
C module generates an internal interrupt that can be routed to the following destinations:
• CPU interrupt, if I2ICR[IE] is set to 1
• TX requestor at the multichannel DMA, if I2ICR[TE] is set to 1
• RX requestor at the multichannel DMA, if I2ICR[RE] is set to 1
The destination for the interrupt is the CPU. The reset condition is to have IE set.
Typically, only one (or none) of the above destinations would be specified, although it may be useful to
send an interrupt to both the CPU and the multichannel DMA. The selection between TX and RX is based
on whether the module is sending data (master or slave TX) or receiving data (master or slave RX).
Individual requestors would trigger different multichannel DMA tasks. The reset condition is to have IE
set, and all other enable bits clear.
An additional bit, BNBE, is provided to permit the module to generate an interrupt when the bus becomes
NOT busy. This implies the receipt of a STOP condition, for which the module normally does not generate
an interrupt. Because bus NOT busy is an IDLE condition, it is necessary for software responding to this
interrupt to clear the BNBE bit in order to clear the interrupt condition, otherwise it will persist until
another IIC transaction is initiated.
The MCF548x contains one I
2
C module. The interrupt control register is common to I
2
C modules.
7 6 5 4 3 2 1 0
R DATA
W
Reset 0 0 0 0 0 0 0 0
Reg
Addr
MBAR + 0x8F10
Figure 28-6. I
2
C Data I/O Register (I2DR)
Table 28-7. I2DR Field Description
Bit Name Description
7–0 DATA I
2
C data. In master transmit mode, when data is written to this register, a data transfer is initiated. The
most significant bit is sent first. In master receive mode, reading this register initiates the reception of
the next byte of data. In slave mode, the same functions are available after an address match has
occurred.
Note: 1. In master transmit mode, the first byte of data written to I2DR following assertion of MSTA
is used for the address transfer and should comprise the calling address (in position D7–D1)
concatenated with the required R/W bit (in position D0). This bit (D0) is not automatically appended
by the hardware, software must provide the appropriate R/W bit.
Note: 2. MSTA generates a start when a master does not already own the bus. RSTA generates a
start (restart) without the master first issuing a stop (i.e., the master already owns the bus). In order
to start the read of data, a dummy read to the MDR starts the read process from the slave. The next
read of the MDR register contains the actual data.