Freescale Semiconductor MCF5480 - Manual (Page 916)

MCF548x Reference Manual, Rev. 3
29-42 Freescale Semiconductor
29.2.5.7 USB Endpoint n FIFO Control Register (EPnFCR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R SHAD 0 WFR TMR FRM GR IP
MSK
FAE
MSK
RXW
MSK
UF
MSK
OF
MSK
TXW
MSK 0 0
W
Reset 0 Unin. 0 0 0 0 0 1 0 0 1 0 0 1 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R COUNTER
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reg
Addr
MBAR + 0xB458 (EP0FCR); 0xB488 (EP1FCR); 0xB4B8 (EP2FCR); 0xB4E8 (EP3FCR);
0xB518 (EP4FCR); 0xB548 (EP5FCR); 0xB578 (EP6FCR)
Figure 29-47. USB Endpoint n FIFO Control Register (EPnFCR)
Table 29-42. EPnFCR Field Descriptions
Bits Name Description
31 SHAD Shadow. In shadow mode, the FIFO frame ready and alarm signals are suppressed until the USB
acknowledges successful transmission or reception of the packet (frame). Shadow mode is a
sub-mode of frame mode, and as such, this bit must be set along with the FRM bit to have any affect
on the FIFO status operation. This bit should be set during normal USB operation.
0 Shadow mode disabled.
1 Shadow mode enabled (FRM bit must also be set).
30 — Reserved, should be cleared.
29 WFR Write end of frame. This determines the end of current data frame in FIFO.
0 Next write to FIFO data register is not the end of frame.
1 Next write to FIFO data register is the end of frame.
28 TMR Timer mode. For OUT (receive) endpoints, timer mode prevents a request for service from occurring
every frame. Instead, a request is made on a periodic basis that is determined by the value that is
programmed into the COUNTER[15:0] field. A request will be made if there is a valid frame in the
FIFO and there has not been a read or write to the FIFO in the specified number of cycles.
Note that requests for service due to the FIFO reaching a high-water mark are not affected by timer
mode and will occur as usual. Timer mode is a sub-mode of frame mode, and as such, this bit must
be set along with the FRM bit to have any affect on the FIFO frame ready operation.
0 Timer mode disabled.
1 Timer mode enabled (FRM bit must also be set).
27 FRM Frame mode. In Frame mode, the FIFO uses its internal frame pointer and information from the
peripheral to transfer only full frames of data, as defined by the peripheral. Because the controller
only keeps a pointer to the end of the last complete frame, a read request may contain more than
one frame of data. This bit should be set during normal USB operation.
0 Frame mode disabled.
1 Frame mode enabled.