Freescale Semiconductor MCF5480 - Manual (Page 942)

MCF548x Reference Manual, Rev. 3
30-12 Freescale Semiconductor
30.3.3.2 Interrupt Mask Register (EIMR)
The EIMR controls which possible interrupt events are allowed to generate actual interrupts. All
implemented bits in this CSR are read/write. This register is cleared upon a hardware reset. If the
corresponding bits in both the EIR and EIMR registers are set, the interrupt will be signalled to the on chip
interrupt controller. The interrupt signal will remain asserted until a 1 is written to the EIR bit (write 1 to
clear) or a 0 is written to the EIMR bit.
26–24 — Reserved, should be cleared.
23 MII MII interrupt. This bit indicates that the MII has completed the data transfer requested. This bit is
cleared by writing a 1 to it.
22 — Reserved, should be cleared.
21 LC Late collison. This bit indicates that a collision occurred beyond the collision window (slot time) in
half duplex mode. The frame is truncated with a bad CRC and the remainder of the frame is
discarded. This bit is cleared by writing a 1 to it.
20 RL Collision retry limit. This bit indicates that a collision occurred on each of 16 successive attempts to
transmit the frame. The frame is discarded without being transmitted and transmission of the next
frame will commence. Can only occur in half duplex mode. This bit is cleared by writing a 1 to it.
19 XFUN Transmit FIFO underrun. This bit indicates that the transmit FIFO became empty before the
complete frame was transmitted. A bad CRC is appended to the frame fragment and the remainder
of the frame is discarded. This bit is cleared by writing a 1 to it.
18 XFERR Transmit FIFO error. This bit indicates that an error has occurred within the transmit FIFO. When the
XFERR bit is set, ECR[ETHER_EN] will be cleared, halting frame processing by the FEC. When this
occurs, software will need to generate a software reset of the FIFO controller. This bit is cleared by
writing a 1 to it.
17 RFERR Receive FIFO error. This bit indicates that an error has occurred within the receive FIFO. When the
RFERR bit is set, ECR[ETHER_EN] will be cleared, halting frame processing by the FEC. When this
occurs, software will need to generate a software reset of the FIFO controller. This bit is cleared by
writing a 1 to it.
16–0 — Reserved, should be cleared.
Table 30-7. EIR Descriptions (Continued)
Bits Name Description