Freescale Semiconductor MCF5480 - Manual (Page 950)

MCF548x Reference Manual, Rev. 3
30-20 Freescale Semiconductor
30.3.3.10 Physical Address Low Register (PALR)
The PALR is written by the user. This register contains the lower 32 bits (bytes 0,1,2,3) of the 48-bit
address used in the address recognition process to compare with the DA (Destination Address) field of
receive frames with an individual DA. In addition, this register is used in bytes 0 through 3 of the 6-byte
source address field when transmitting PAUSE frames. This register is not reset and must be initialized by
the user.
Table 30-16. TCR Field Descriptions
Bits Name Description
31–5 — Reserved, should be cleared.
4 RFC_PAUSE Receive frame control pause. This read-only status bit will be set when a full duplex flow control
pause frame has been received and the transmitter is paused for the duration defined in this
pause frame. This bit will automatically clear when the pause duration is complete.
3 TFC_PAUSE Transmit frame control pause. Transmits a PAUSE frame when set. When this bit is set, the MAC
will stop transmission of data frames after the current transmission is complete. At this time, the
GRA interrupt in the EIR register will be asserted. With transmission of data frames stopped, the
MAC will transmit a MAC Control PAUSE frame. Next, the MAC will clear the TFC_PAUSE bit and
resume transmitting data frames. Note that if the transmitter is paused due to user assertion of
GTS or reception of a PAUSE frame, the MAC may still transmit a MAC Control PAUSE frame.
2 FDEN Full duplex enable. If set, frames are transmitted independent of carrier sense and collision inputs.
This bit should only be modified when ETHER_EN is deasserted.
1 HBC Heartbeat control. If set, the heartbeat check is performed following end of transmission and the
HBERR bit in the EIR will be set if the collision input does not assert within the heartbeat window.
This bit should only be modified when ETHER_EN is deasserted.
0 GTS Graceful transmit stop. When this bit is set, the MAC will stop transmission after any frame that is
currently being transmitted is complete and the GRA interrupt in the EIR register will be asserted.
If frame transmission is not currently underway, the GRA interrupt will be asserted immediately.
Once transmission has completed, a “restart” can be accomplished by clearing the GTS bit. The
next frame in the transmit FIFO will then be transmitted. If an early collision occurs during
transmission when GTS = 1, transmission will stop after the collision. The frame will be transmitted
again once GTS is cleared. Note that there may be old frames in the transmit FIFO that will be
transmitted when GTS is reasserted. To avoid this, deassert ECR[ETHER_EN] following the GRA
interrupt.