12 opcode/pause duration register (opd), 13 individual address upper register (iaur), Opcode/pause duration register (opd) -22 – Freescale Semiconductor MCF5480 User Manual
Page 952: Individual address upper register (iaur) -22
MCF548x Reference Manual, Rev. 3
30-22
Freescale Semiconductor
30.3.3.12 Opcode/Pause Duration Register (OPD)
The OPD is read/write accessible. This register contains the 16-bit opcode and 16-bit pause duration fields
used in transmission of a PAUSE frame. The OPCODE field is a constant value, 0x0001. When another
node detects a PAUSE frame, that node will pause transmission for the duration specified in the pause
duration field. This register is not reset and must be initialized by the user.
30.3.3.13 Individual Address Upper Register (IAUR)
The IAUR is written by the user. This register contains the upper 32 bits of the 64-bit individual address
hash table used in the address recognition process to check for possible match with the destination address
(DA) field of receive frames with an individual DA. This register is not reset and must be initialized by
the user.
Table 30-18. PAHR Field Descriptions
BIts
Name
Description
31–16
PADDR2
Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address to be used for exact
match, and the Source Address field in PAUSE frames.
15–0
TYPE
Type field in PAUSE frames. These 16-bits are a constant value of 0x8808.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
OPCODE
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
PAUSE_DUR
W
Reset
Uninitialized
Reg
Addr
MBAR + 0x90EC (FEC0), 0x98EC (FEC1)
Figure 30-13. Opcode/Pause Duration Register (OPD)
Table 30-19. OPD Field Descriptions
Bits
Name
Description
31–16
OPCODE
Opcode field used in PAUSE frames. These bits are a constant: 0x0001.
15–0
PAUSE_DUR
Pause Duration field used in PAUSE frames.