17 fec transmit fifo watermark register (fectfwr), Fec transmit fifo watermark register (fectfwr) -25 – Freescale Semiconductor MCF5480 User Manual

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Memory Map/Register Definition

MCF548x Reference Manual, Rev. 3

Freescale Semiconductor

30-25

30.3.3.17 FEC Transmit FIFO Watermark Register (FECTFWR)

The FECTFWR is a 32-bit read/write register programmed by the user to control the amount of data

required in the transmit FIFO before transmission of a frame can begin. This allows the user to minimize

transmit latency or allow for larger bus access latency due to contention for the system bus. Setting the

watermark to a high value will minimize the risk of transmit FIFO underrun due to contention for the

system bus. The byte counts associated with the X_WMRK field may need to be modified to match a given

system requirement (worst case bus access latency by the transmit data DMA channel). This register

should be programmed so that the selected number of bytes is less than or equal to the number of bytes

indicated in the transmit FIFO alarm register, FECTFAR.
Both the transmit and receive FIFOs are 1024 bytes deep.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

R

GADDR2

W

Reset

Uninitialized

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R

GADDR2

W

Reset

Uninitialized

Reg

Addr

MBAR + 0x9124 (FEC0), 0x9924 (FEC1)

Figure 30-19. Group Address Lower Register (GALR)

Table 30-23. GALR Field Descriptions

Bits

Name

Description

31–0

GADDR2

Group Address Lower - The GADDR2 register contains the lower 32 bits of the 64-bit hash
table used in the address recognition process for receive frames with a multicast address.
Bit 31 of GADDR2 contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

R

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R

0

0

0

0

0

0

0

0

0

0

0

0

X_WMRK

W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Reg

Addr

MBAR + 0x9144 (FEC0), 0x9944 (FEC1)

Figure 30-20. FEC Transmit FIFO Watermark Register (FECTFWR)

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