26 fec transmit fifo data register (fectfdr), Fec transmit fifo data register (fectfdr) -33 – Freescale Semiconductor MCF5480 User Manual
Page 963
Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
30-33
30.3.3.25 FEC Receive FIFO Write Pointer Register (FECRFWP)
The write pointer is a FIFO maintained pointer which points to the next FIFO location to be written. The
write pointer can be both read and written. This ability facilitates the debug of the FIFO controller and
peripheral drivers. The write pointer is reset to zero, and non-functional bits of this pointer will always
remain zero.
30.3.3.26 FEC Transmit FIFO Data Register (FECTFDR)
This is the main interface port for the FIFO. Data which is to be buffered in the FIFO or has been buffered
in the FIFO, is accessed through this register. It can be accessed by byte, word, or longword. It is
recommended to align all accesses to the most significant byte (big endian) of the data port, using the
address of TFDR for byte, word, and longword transactions. However, accessing the data port at TFDR+1,
2, or 3 for bytes or TFDR+2 for words is also acceptable. This register is usually read without wait state,
but can be held under boundary conditions.
Table 30-31. FECRFRP Field Descriptions
Bits
Name
Descriptions
31–10
—
Reserved, should be cleared.
9–0
READ
Read pointer. This pointer indicates the next location to be read by the FIFO controller.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
WRITE
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x91A0 (FEC0), 0x99A0 (FEC1)
Figure 30-28. FEC Receive FIFO Write Pointer Register (FECRFWP)
Table 30-32. FECRFWP Field Descriptions
Bits
Name
Descriptions
31–10
—
Reserved, should be cleared.
9–0
WRITE
Write pointer. This pointer indicates the next location to be written by the FIFO controller.