Freescale Semiconductor MCF5480 - Manual (Page 984)

MCF548x Reference Manual, Rev. 3
30-54 Freescale Semiconductor
transmit side and/or limit the size of the frames to prevent transmit FIFO underrun and receive FIFO
overflow.
For external loopback set RCR[LOOP] = 0, RCR[DRT] = 0 and configure the external transceiver for
loopback.
30.4.12 Ethernet Error-Handling Procedure
The Ethernet controller reports frame reception and transmission error conditions using the receive frame
status words (RFSWs), the EIR register, and the MIB block counters.
30.4.12.1 Transmission Errors
30.4.12.1.1 Transmitter Underrun
If this error occurs, the FEC sends 32 bits that ensure a CRC error and stops transmitting. The XFUN bit
is set in the EIR. The FEC will then continue to the next transmit buffer descriptor and begin transmitting
the next frame.
The XFUN interrupt will be asserted if enabled in the EIMR register.
30.4.12.1.2 Retransmission Attempts Limit Expired
When this error occurs, the FEC terminates transmission. The RL bit is set in the EIR. The FEC will then
begin transmitting the next frame.
The “RL” interrupt will be asserted if enabled in the EIMR register.
30.4.12.1.3 Late Collision
When a collision occurs after the slot time (512 bits starting at the Preamble), the FEC terminates
transmission. All remaining data in the frame is discarded, and the LC bit is set in the EIR register. The
FEC will then continue to the next transmit buffer descriptor and begin transmitting the next frame.
The “LC” interrupt will be asserted if enabled in the EIMR register.
30.4.12.1.4 Heartbeat
Some transceivers have a self-test feature called “heartbeat” or “signal quality error.” To signify a good
self-test, the transceiver indicates a collision to the FEC within 4 microseconds after completion of a frame
transmitted by the Ethernet controller. This indication of a collision does not imply a real collision error
on the network, but is rather an indication that the transceiver still seems to be functioning properly. This
is called the heartbeat condition.
If the HBC bit is set in the TCR register and the heartbeat condition is not detected by the FEC after a
frame transmission, then a heartbeat error occurs. When this error occurs, the FEC generates the HBERR
interrupt if it is enabled.