Document Outline

• Features
• 1. Description
• 2. AT91CAP9S500A/AT91CAP9S250A Block Diagram
• 3. Signal Description
• 4. Package and Pinout
  • 4.1 400-ball BGA Package Outline
  • 4.2 400-ball BGA Package Pinout
• 5. Power Considerations
  • 5.1 Power Supplies
  • 5.2 Power Consumption
  • 5.3 Programmable I/O Lines Power Supplies
• 6. I/O Line Considerations
  • 6.1 JTAG Port Pins
  • 6.2 Test Pin
  • 6.3 Reset Pins
  • 6.4 PIO Controllers
  • 6.5 Shutdown Logic Pins
• 7. Processor and Architecture
  • 7.1 ARM926EJ-S Processor
  • 7.2 Bus Matrix
  • 7.3 Matrix Masters
  • 7.4 Matrix Slaves
  • 7.5 Master-to-Slave Access
  • 7.6 Peripheral DMA Controller
  • 7.7 DMA Controller
  • 7.8 Debug and Test Features
• 8. Memories
  • 8.1 Embedded Memories
    • 8.1.1 Internal Memory Mapping
    • 8.1.2 Boot Program
  • 8.2 External Memories
    • 8.2.1 External Bus Interface
    • 8.2.2 Static Memory Controller
    • 8.2.3 DDR/SDRAM Controller
    • 8.2.4 Burst Cellular RAM Controller
    • 8.2.5 Error Corrected Code Controller
• 9. System Controller
  • 9.1 System Controller Block Diagram
  • 9.2 Reset Controller
  • 9.3 Shutdown Controller
  • 9.4 Clock Generator
  • 9.5 Power Management Controller
  • 9.6 Periodic Interval Timer
  • 9.7 Watchdog Timer
  • 9.8 Real-time Timer
  • 9.9 General-Purpose Backed-up Registers
  • 9.10 Advanced Interrupt Controller
  • 9.11 Debug Unit
  • 9.12 Chip Identification
  • 9.13 PIO Controllers
• 10. Peripherals
  • 10.1 User Interface
  • 10.2 Identifiers
    • 10.2.1 Peripheral Interrupts and Clock Control
  • 10.3 Peripherals Signals Multiplexing on I/O Lines
    • 10.3.1 PIO Controller A Multiplexing
    • 10.3.2 PIO Controller B Multiplexing
    • 10.3.3 PIO Controller C Multiplexing
    • 10.3.4 PIO Controller D Multiplexing
  • 10.4 Embedded Peripherals
    • 10.4.1 Serial Peripheral Interface
    • 10.4.2 Two-wire Interface
    • 10.4.3 USART
    • 10.4.4 Synchronous Serial Controller
    • 10.4.5 AC97 Controller
    • 10.4.6 Timer Counter
    • 10.4.7 Pulse Width Modulation Controller
    • 10.4.8 Multimedia Card Interface
    • 10.4.9 CAN Controller
    • 10.4.10 USB Host Port
    • 10.4.11 USB High Speed Device Port
    • 10.4.12 LCD Controller
    • 10.4.13 Ethernet 10/100 MAC
    • 10.4.14 Image Sensor Interface
• 11. Metal Programmable Block
  • 11.1 Internal Connectivity
    • 11.1.1 Clocks
    • 11.1.2 AHB Master Buses
    • 11.1.3 AHB Slave Buses
    • 11.1.4 Interrupts
    • 11.1.5 DMA Channels
    • 11.1.6 Peripheral DMA Channels
    • 11.1.7 MPBlock Single Port RAMs
    • 11.1.8 MPBlock Dual Port RAMs
    • 11.1.9 Optional Peripherals Enable
  • 11.2 External Connectivity
    • 11.2.1 Dedicated I/O Lines
    • 11.2.2 UTMI+ Transceiver
  • 11.3 Prototyping Solution
• 12. ARM926EJ-S Processor Overview
  • 12.1 Overview
  • 12.2 Block Diagram
  • 12.3 ARM9EJ-S Processor
    • 12.3.1 ARM9EJ-S Operating States
    • 12.3.2 Switching State
    • 12.3.3 Instruction Pipelines
    • 12.3.4 Memory Access
    • 12.3.5 Jazelle Technology
    • 12.3.6 ARM9EJ-S Operating Modes
    • 12.3.7 ARM9EJ-S Registers
    • 12.3.8 ARM Instruction Set Overview
    • 12.3.9 New ARM Instruction Set
    • 12.3.10 Thumb Instruction Set Overview
  • 12.4 CP15 Coprocessor
    • 12.4.1 CP15 Registers Access
  • 12.5 Memory Management Unit (MMU)
    • 12.5.1 Access Control Logic
    • 12.5.2 Translation Look-aside Buffer (TLB)
    • 12.5.3 Translation Table Walk Hardware
    • 12.5.4 MMU Faults
  • 12.6 Caches and Write Buffer
    • 12.6.1 Instruction Cache (ICache)
    • 12.6.2 Data Cache (DCache) and Write Buffer
  • 12.7 Tightly-Coupled Memory Interface
    • 12.7.1 TCM Description
    • 12.7.2 Enabling and Disabling TCMs
    • 12.7.3 TCM Mapping
  • 12.8 Bus Interface Unit
    • 12.8.1 Supported Transfers
    • 12.8.2 Thumb Instruction Fetches
    • 12.8.3 Address Alignment
• 13. Debug and Test
  • 13.1 Description
  • 13.2 Block Diagram
  • 13.3 Application Examples
    • 13.3.1 Debug Environment
    • 13.3.2 Test Environment
  • 13.4 Debug and Test Pin Description
  • 13.5 Functional Description
    • 13.5.1 Test Pin
    • 13.5.2 Embedded In-circuit Emulator
    • 13.5.3 JTAG Signal Description
    • 13.5.4 Debug Unit
    • 13.5.5 IEEE 1149.1 JTAG Boundary Scan
    • 13.5.6 ID Code Register
• 14. Boot Program
  • 14.1 Description
  • 14.2 Flow Diagram
  • 14.3 Device Initialization
  • 14.4 DataFlash Boot
    • 14.4.1 Valid Image Detection
    • 14.4.2 Structure of ARM Vector 6
    • 14.4.3 DataFlash Boot Sequence
  • 14.5 NANDFlash Boot
    • 14.5.1 Supported NANDFlash Devices
  • 14.6 SAM-BA Boot
    • 14.6.1 DBGU Serial Port
    • 14.6.2 Xmodem Protocol
    • 14.6.3 USB Device Port
  • 14.7 Hardware and Software Constraints
• 15. Reset Controller (RSTC)
  • 15.1 Description
  • 15.2 Block Diagram
  • 15.3 Functional Description
    • 15.3.1 Reset Controller Overview
    • 15.3.2 NRST Manager
    • 15.3.3 BMS Sampling
    • 15.3.4 Reset States
    • 15.3.5 Reset State Priorities
    • 15.3.6 Reset Controller Status Register
  • 15.4 Reset Controller (RSTC) User Interface
    • 15.4.1 Reset Controller Control Register
    • 15.4.2 Reset Controller Status Register
    • 15.4.3 Reset Controller Mode Register
• 16. Real-time Timer (RTT)
  • 16.1 Overview
  • 16.2 Block Diagram
  • 16.3 Functional Description
  • 16.4 Real-time Timer (RTT) User Interface
    • 16.4.1 Real-time Timer Mode Register
    • 16.4.2 Real-time Timer Alarm Register
    • 16.4.3 Real-time Timer Value Register
    • 16.4.4 Real-time Timer Status Register
• 17. Periodic Interval Timer (PIT)
  • 17.1 Overview
  • 17.2 Block Diagram
  • 17.3 Functional Description
  • 17.4 Periodic Interval Timer (PIT) User Interface
    • 17.4.1 Periodic Interval Timer Mode Register
    • 17.4.2 Periodic Interval Timer Status Register
    • 17.4.3 Periodic Interval Timer Value Register
    • 17.4.4 Periodic Interval Timer Image Register
• 18. Watchdog Timer (WDT)
  • 18.1 Description
  • 18.2 Block Diagram
  • 18.3 Functional Description
  • 18.4 Watchdog Timer (WDT) User Interface
    • 18.4.1 Watchdog Timer Control Register
    • 18.4.2 Watchdog Timer Mode Register
    • 18.4.3 Watchdog Timer Status Register
• 19. Shutdown Controller (SHDWC)
  • 19.1 Description
  • 19.2 Block Diagram
  • 19.3 I/O Lines Description
  • 19.4 Product Dependencies
    • 19.4.1 Power Management
  • 19.5 Functional Description
  • 19.6 Shutdown Controller (SHDWC) User Interface
    • 19.6.1 Register Mapping
    • 19.6.2 Shutdown Control Register
    • 19.6.3 Shutdown Mode Register
    • 19.6.4 Shutdown Status Register
• 20. Bus Matrix
  • 20.1 Description
  • 20.2 Memory Mapping
  • 20.3 Special Bus Granting Techniques
    • 20.3.1 No Default Master
    • 20.3.2 Last Access Master
    • 20.3.3 Fixed Default Master
  • 20.4 Arbitration
    • 20.4.1 Arbitration Rules
    • 20.4.2 Round-Robin Arbitration
    • 20.4.3 Fixed Priority Arbitration
  • 20.5 Bus Matrix User Interface
    • 20.5.1 Bus Matrix Master Configuration Registers
    • 20.5.2 Bus Matrix Slave Configuration Registers
    • 20.5.3 Bus Matrix Priority Registers A For Slaves
    • 20.5.4 Bus Matrix Priority Registers B For Slaves
    • 20.5.5 Bus Matrix Master Remap Control Register
  • 20.6 Chip Configuration User Interface
    • 20.6.1 MPBlock Slave 0 Special Function Register
    • 20.6.2 MPBlock Slave 1 Special Function Register
    • 20.6.3 EBI Chip Select Assignment Register
    • 20.6.4 MPBlock Slave 2 Special Function Register
    • 20.6.5 MPBlock Slave 3 Special Function Register
    • 20.6.6 APB Bridge Special Function Register
• 21. External Bus Interface (EBI)
  • 21.1 Description
    • 21.1.1 External Bus Interface
  • 21.2 I/O Lines Description
  • 21.3 Application Example
    • 21.3.1 Hardware Interface
  • 21.4 Product Dependencies
    • 21.4.1 I/O Lines
  • 21.5 Functional Description
    • 21.5.1 Bus Multiplexing
    • 21.5.2 Pull-up Control
    • 21.5.3 Supply Control
    • 21.5.4 Static Memory Controller
    • 21.5.5 DDR/SDRAM Controller
    • 21.5.6 BCRAM Controller
    • 21.5.7 ECC Controller
    • 21.5.8 CompactFlash Support
    • 21.5.9 NAND Flash Support
  • 21.6 Implementation Examples
    • 21.6.1 16-bit SDRAM
    • 21.6.2 32-bit SDRAM
    • 21.6.3 16-bit Mobile DDR
    • 21.6.4 16-bit BCRAM
    • 21.6.5 8-bit NAND Flash
    • 21.6.6 16-bit NAND Flash
    • 21.6.7 NOR Flash on NCS0
    • 21.6.8 Compact Flash
    • 21.6.9 Compact Flash True IDE
• 22. Static Memory Controller (SMC)
  • 22.1 Description
  • 22.2 I/O Lines Description
  • 22.3 Multiplexed Signals
  • 22.4 Application Example
    • 22.4.1 Hardware Interface
  • 22.5 Product Dependencies
    • 22.5.1 I/O Lines
  • 22.6 External Memory Mapping
  • 22.7 Connection to External Devices
    • 22.7.1 Data Bus Width
    • 22.7.2 Byte Write or Byte Select Access
  • 22.8 Standard Read and Write Protocols
    • 22.8.1 Read Waveforms
    • 22.8.2 Read Mode
    • 22.8.3 Write Waveforms
    • 22.8.4 Write Mode
    • 22.8.5 Coding Timing Parameters
    • 22.8.6 Reset Values of Timing Parameters
    • 22.8.7 Usage Restriction
  • 22.9 Automatic Wait States
    • 22.9.1 Chip Select Wait States
    • 22.9.2 Early Read Wait State
    • 22.9.3 Reload User Configuration Wait State
    • 22.9.4 Read to Write Wait State
  • 22.10 Data Float Wait States
    • 22.10.1 READ_MODE
    • 22.10.2 TDF Optimization Enabled (TDF_MODE = 1)
    • 22.10.3 TDF Optimization Disabled (TDF_MODE = 0)
  • 22.11 External Wait
    • 22.11.1 Restriction
    • 22.11.2 Frozen Mode
    • 22.11.3 Ready Mode
    • 22.11.4 NWAIT Latency and Read/write Timings
  • 22.12 Slow Clock Mode
    • 22.12.1 Slow Clock Mode Waveforms
    • 22.12.2 Switching from (to) Slow Clock Mode to (from) Normal Mode
  • 22.13 Asynchronous Page Mode
    • 22.13.1 Protocol and Timings in Page Mode
    • 22.13.2 Byte Access Type in Page Mode
    • 22.13.3 Page Mode Restriction
    • 22.13.4 Sequential and Non-sequential Accesses
  • 22.14 Static Memory Controller (SMC) User Interface
    • 22.14.1 SMC Setup Register
    • 22.14.2 SMC Pulse Register
    • 22.14.3 SMC Cycle Register
    • 22.14.4 SMC MODE Register
• 23. DDR/SDR SDRAM Controller (DDRSDRC)
  • 23.1 Description
  • 23.2 DDRSDRC Module Diagram
  • 23.3 Product Dependencies
    • 23.3.1 SDR-SDRAM Initialization
    • 23.3.2 DDR-SDRAM Initialization
    • 23.3.3 Mobile DDR-SDRAM Initialization
  • 23.4 Functional Description
    • 23.4.1 SDRAM Controller Write Cycle
    • 23.4.2 SDRAM Controller Read Cycle
    • 23.4.3 Refresh (Auto-refresh Command)
    • 23.4.4 Power Management
  • 23.5 Software Interface / SDRAM Organization, Address Mapping
    • 23.5.1 SDRAM Address Mapping for 16-bit Memory Data Bus Width(1)
    • 23.5.2 SDR-SDRAM Address Mapping for 32-bit Memory Data Bus Width
  • 23.6 DDR-SDRAMC User Interface
    • 23.6.1 DDRSDRC Mode Register
    • 23.6.2 DDRSDRC Refresh Timer Register
    • 23.6.3 DDRSDRC Configuration Register
    • 23.6.4 DDRSDRC Timing 0 Parameter Register
    • 23.6.5 DDRSDRC Timing 1 Parameter Register
    • 23.6.6 DDRSDRC Low-power Register
    • 23.6.7 DDRSDRC Memory Device Register
    • 23.6.8 DDRSDRC DLL Information
• 24. Burst Cellular RAM Controller (BCRAMC)
  • 24.1 Description
  • 24.2 BCRAMC Block Diagram
  • 24.3 Product Dependencies
    • 24.3.1 Cellular Ram Initialization
  • 24.4 Functional Description
    • 24.4.1 BCRAMC Overview
    • 24.4.2 BCRAMC Write Cycle
    • 24.4.3 BCRAMC Read Cycle
    • 24.4.4 Power Management
  • 24.5 BCRAMC User Interface
    • 24.5.1 BCRAMC Configuration Register
    • 24.5.2 BCRAMC Timing Register
    • 24.5.3 BCRAMC Low Power Register
    • 24.5.4 BCRAMC Memory Device Register
    • 24.5.5 BCRAMC ADDRSIZE Register
    • 24.5.6 BCRAMC Name1 Register
    • 24.5.7 BCRAMC Name2 Register
    • 24.5.8 BCRAMC Features Register
• 25. Error Corrected Code (ECC) Controller
  • 25.1 Description
  • 25.2 Block Diagram
  • 25.3 Functional Description
    • 25.3.1 Write Access
    • 25.3.2 Read Access
  • 25.4 Error Corrected Code (ECC) Controller User Interface
    • 25.4.1 ECC Control Register
    • 25.4.2 ECC Mode Register
    • 25.4.3 ECC Status Register
    • 25.4.4 ECC Parity Register
    • 25.4.5 ECC NParity Register
• 26. DMA Controller (DMAC)
  • 26.1 Description
  • 26.2 Block Diagram
  • 26.3 Functional Description
    • 26.3.1 Basic Definitions
    • 26.3.2 Memory Peripherals
    • 26.3.3 Handshaking Interface
    • 26.3.4 DMAC Transfer Types
    • 26.3.5 Programming a Channel
    • 26.3.6 Disabling a Channel Prior to Transfer Completion
  • 26.4 DMA Controller Software Requirements
  • 26.5 DMA Controller (DMAC) User Interface
    • 26.5.1 DMAC Global Configuration Register
    • 26.5.2 DMAC Enable Register
    • 26.5.3 DMAC Software Single Request Register
    • 26.5.4 DMAC Software Chunk Transfer Request Register
    • 26.5.5 DMAC Software Last Transfer Flag Register
    • 26.5.6 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register
    • 26.5.7 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register
    • 26.5.8 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register
    • 26.5.9 DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register
    • 26.5.10 DMAC Channel Handler Enable Register
    • 26.5.11 DMAC Channel Handler Disable Register
    • 26.5.12 DMAC Channel Handler Status Register
    • 26.5.13 DMAC Channel x [x = 0..3] Source Address Register
    • 26.5.14 DMAC Channel x [x = 0..3] Destination Address Register
    • 26.5.15 DMAC Channel x [x = 0..3] Descriptor Address Register
    • 26.5.16 DMAC Channel x [x = 0..3] Control A Register
    • 26.5.17 DMAC Channel x [x = 0..3] Control B Register
    • 26.5.18 DMAC Channel x [x = 0..3] Configuration Register
    • 26.5.19 DMAC Channel x [x = 0..3] Source Picture in Picture Configuration Register
    • 26.5.20 DMAC Channel x [x = 0..3] Destination Picture in Picture Configuration Register
• 27. Peripheral DMA Controller (PDC)
  • 27.1 Description
  • 27.2 Block Diagram
  • 27.3 Functional Description
    • 27.3.1 Configuration
    • 27.3.2 Memory Pointers
    • 27.3.3 Transfer Counters
    • 27.3.4 Data Transfers
    • 27.3.5 PDC Flags and Peripheral Status Register
  • 27.4 Peripheral DMA Controller (PDC) User Interface
    • 27.4.1 Receive Pointer Register
    • 27.4.2 Receive Counter Register
    • 27.4.3 Transmit Pointer Register
    • 27.4.4 Transmit Counter Register
    • 27.4.5 Receive Next Pointer Register
    • 27.4.6 Receive Next Counter Register
    • 27.4.7 Transmit Next Pointer Register
    • 27.4.8 Transmit Next Counter Register
    • 27.4.9 Transfer Control Register
    • 27.4.10 Transfer Status Register
• 28. Clock Generator
  • 28.1 Description
  • 28.2 Slow Clock Crystal Oscillator
  • 28.3 Main Oscillator
    • 28.3.1 Main Oscillator Connections
    • 28.3.2 Main Oscillator Startup Time
    • 28.3.3 Main Oscillator Control
    • 28.3.4 Main Clock Frequency Counter
    • 28.3.5 Main Oscillator Bypass
  • 28.4 Divider and PLL Block
    • 28.4.1 PLL Filter
    • 28.4.2 Divider and Phase Lock Loop Programming
    • 28.4.3 UTMI Phase Lock Loop Programming
• 29. Power Management Controller (PMC)
  • 29.1 Description
  • 29.2 Master Clock Controller
  • 29.3 Processor Clock Controller
  • 29.4 USB Clock Controller
  • 29.5 Peripheral Clock Controller
  • 29.6 Programmable Clock Output Controller
  • 29.7 Programming Sequence
  • 29.8 Clock Switching Details
    • 29.8.1 Master Clock Switching Timings
    • 29.8.2 Clock Switching Waveforms
  • 29.9 Power Management Controller (PMC) User Interface
    • 29.9.1 PMC System Clock Enable Register
    • 29.9.2 PMC System Clock Disable Register
    • 29.9.3 PMC System Clock Status Register
    • 29.9.4 PMC Peripheral Clock Enable Register
    • 29.9.5 PMC Peripheral Clock Disable Register
    • 29.9.6 PMC Peripheral Clock Status Register
    • 29.9.7 PMC UTMI Clock Configuration Register
    • 29.9.8 PMC Clock Generator Main Oscillator Register
    • 29.9.9 PMC Clock Generator Main Clock Frequency Register
    • 29.9.10 PMC Clock Generator PLL A Register
    • 29.9.11 PMC Clock Generator PLL B Register
    • 29.9.12 PMC Master Clock Register
    • 29.9.13 PMC Programmable Clock Register
    • 29.9.14 PMC Interrupt Enable Register
    • 29.9.15 PMC Interrupt Disable Register
    • 29.9.16 PMC Status Register
    • 29.9.17 PMC Interrupt Mask Register
• 30. Advanced Interrupt Controller (AIC)
  • 30.1 Description
  • 30.2 Block Diagram
  • 30.3 Application Block Diagram
  • 30.4 AIC Detailed Block Diagram
  • 30.5 I/O Line Description
  • 30.6 Product Dependencies
    • 30.6.1 I/O Lines
    • 30.6.2 Power Management
    • 30.6.3 Interrupt Sources
  • 30.7 Functional Description
    • 30.7.1 Interrupt Source Control
    • 30.7.2 Interrupt Latencies
    • 30.7.3 Normal Interrupt
    • 30.7.4 Fast Interrupt
    • 30.7.5 Protect Mode
    • 30.7.6 Spurious Interrupt
    • 30.7.7 General Interrupt Mask
  • 30.8 Advanced Interrupt Controller (AIC) User Interface
    • 30.8.1 Base Address
    • 30.8.2 Register Mapping
    • 30.8.3 AIC Source Mode Register
    • 30.8.4 AIC Source Vector Register
    • 30.8.5 AIC Interrupt Vector Register
    • 30.8.6 AIC FIQ Vector Register
    • 30.8.7 AIC Interrupt Status Register
    • 30.8.8 AIC Interrupt Pending Register
    • 30.8.9 AIC Interrupt Mask Register
    • 30.8.10 AIC Core Interrupt Status Register
    • 30.8.11 AIC Interrupt Enable Command Register
    • 30.8.12 AIC Interrupt Disable Command Register
    • 30.8.13 AIC Interrupt Clear Command Register
    • 30.8.14 AIC Interrupt Set Command Register
    • 30.8.15 AIC End of Interrupt Command Register
    • 30.8.16 AIC Spurious Interrupt Vector Register
    • 30.8.17 AIC Debug Control Register
    • 30.8.18 AIC Fast Forcing Enable Register
    • 30.8.19 AIC Fast Forcing Disable Register
    • 30.8.20 AIC Fast Forcing Status Register
• 31. Debug Unit (DBGU)
  • 31.1 Description
  • 31.2 Block Diagram
  • 31.3 Product Dependencies
    • 31.3.1 I/O Lines
    • 31.3.2 Power Management
    • 31.3.3 Interrupt Source
  • 31.4 UART Operations
    • 31.4.1 Baud Rate Generator
    • 31.4.2 Receiver
    • 31.4.3 Transmitter
    • 31.4.4 Peripheral Data Controller
    • 31.4.5 Test Modes
    • 31.4.6 Debug Communication Channel Support
    • 31.4.7 Chip Identifier
    • 31.4.8 ICE Access Prevention
  • 31.5 Debug Unit User Interface
    • 31.5.1 Debug Unit Control Register
    • 31.5.2 Debug Unit Mode Register
    • 31.5.3 Debug Unit Interrupt Enable Register
    • 31.5.4 Debug Unit Interrupt Disable Register
    • 31.5.5 Debug Unit Interrupt Mask Register
    • 31.5.6 Debug Unit Status Register
    • 31.5.7 Debug Unit Receiver Holding Register
    • 31.5.8 Debug Unit Transmit Holding Register
    • 31.5.9 Debug Unit Baud Rate Generator Register
    • 31.5.10 Debug Unit Chip ID Register
    • 31.5.11 Debug Unit Chip ID Extension Register
    • 31.5.12 Debug Unit Force NTRST Register
• 32. Parallel Input/Output Controller (PIO)
  • 32.1 Description
  • 32.2 Block Diagram
  • 32.3 Product Dependencies
    • 32.3.1 Pin Multiplexing
    • 32.3.2 External Interrupt Lines
    • 32.3.3 Power Management
    • 32.3.4 Interrupt Generation
  • 32.4 Functional Description
    • 32.4.1 Pull-up Resistor Control
    • 32.4.2 I/O Line or Peripheral Function Selection
    • 32.4.3 Peripheral A or B Selection
    • 32.4.4 Output Control
    • 32.4.5 Synchronous Data Output
    • 32.4.6 Multi Drive Control (Open Drain)
    • 32.4.7 Output Line Timings
    • 32.4.8 Inputs
    • 32.4.9 Input Glitch Filtering
    • 32.4.10 Input Change Interrupt
  • 32.5 I/O Lines Programming Example
  • 32.6 User Interface
    • 32.6.1 PIO Controller PIO Enable Register
    • 32.6.2 PIO Controller PIO Disable Register
    • 32.6.3 PIO Controller PIO Status Register
    • 32.6.4 PIO Controller Output Enable Register
    • 32.6.5 PIO Controller Output Disable Register
    • 32.6.6 PIO Controller Output Status Register
    • 32.6.7 PIO Controller Input Filter Enable Register
    • 32.6.8 PIO Controller Input Filter Disable Register
    • 32.6.9 PIO Controller Input Filter Status Register
    • 32.6.10 PIO Controller Set Output Data Register
    • 32.6.11 PIO Controller Clear Output Data Register
    • 32.6.12 PIO Controller Output Data Status Register
    • 32.6.13 PIO Controller Pin Data Status Register
    • 32.6.14 PIO Controller Interrupt Enable Register
    • 32.6.15 PIO Controller Interrupt Disable Register
    • 32.6.16 PIO Controller Interrupt Mask Register
    • 32.6.17 PIO Controller Interrupt Status Register
    • 32.6.18 PIO Multi-driver Enable Register
    • 32.6.19 PIO Multi-driver Disable Register
    • 32.6.20 PIO Multi-driver Status Register
    • 32.6.21 PIO Pull Up Disable Register
    • 32.6.22 PIO Pull Up Enable Register
    • 32.6.23 PIO Pull Up Status Register
    • 32.6.24 PIO Peripheral A Select Register
    • 32.6.25 PIO Peripheral B Select Register
    • 32.6.26 PIO Peripheral A B Status Register
    • 32.6.27 PIO Output Write Enable Register
    • 32.6.28 PIO Output Write Disable Register
    • 32.6.29 PIO Output Write Status Register
• 33. Serial Peripheral Interface (SPI)
  • 33.1 Description
  • 33.2 Block Diagram
  • 33.3 Application Block Diagram
  • 33.4 Signal Description
  • 33.5 Product Dependencies
    • 33.5.1 I/O Lines
    • 33.5.2 Power Management
    • 33.5.3 Interrupt
  • 33.6 Functional Description
    • 33.6.1 Modes of Operation
    • 33.6.2 Data Transfer
    • 33.6.3 Master Mode Operations
    • 33.6.4 SPI Slave Mode
  • 33.7 Serial Peripheral Interface (SPI) User Interface
    • 33.7.1 SPI Control Register
    • 33.7.2 SPI Mode Register
    • 33.7.3 SPI Receive Data Register
    • 33.7.4 SPI Transmit Data Register
    • 33.7.5 SPI Status Register
    • 33.7.6 SPI Interrupt Enable Register
    • 33.7.7 SPI Interrupt Disable Register
    • 33.7.8 SPI Interrupt Mask Register
    • 33.7.9 SPI Chip Select Register
• 34. Two-wire Interface (TWI)
  • 34.1 Description
  • 34.2 List of Abbreviations
  • 34.3 Block Diagram
  • 34.4 Application Block Diagram
    • 34.4.1 I/O Lines Description
  • 34.5 Product Dependencies
    • 34.5.1 I/O Lines
    • 34.5.2 Power Management
    • 34.5.3 Interrupt
  • 34.6 Functional Description
    • 34.6.1 Transfer Format
    • 34.6.2 Modes of Operation
  • 34.7 Master Mode
    • 34.7.1 Definition
    • 34.7.2 Application Block Diagram
    • 34.7.3 Programming Master Mode
    • 34.7.4 Master Transmitter Mode
    • 34.7.5 Master Receiver Mode
    • 34.7.6 Internal Address
    • 34.7.7 Using the Peripheral DMA Controller (PDC)
    • 34.7.8 Read/Write Flowcharts
  • 34.8 Multi-master Mode
    • 34.8.1 Definition
    • 34.8.2 Different Multi-master Modes
  • 34.9 Slave Mode
    • 34.9.1 Definition
    • 34.9.2 Application Block Diagram
    • 34.9.3 Programming Slave Mode
    • 34.9.4 Receiving Data
    • 34.9.5 Data Transfer
    • 34.9.6 Read Write Flowcharts
  • 34.10 Two-wire Interface (TWI) User Interface
    • 34.10.1 TWI Control Register
    • 34.10.2 TWI Master Mode Register
    • 34.10.3 TWI Slave Mode Register
    • 34.10.4 TWI Internal Address Register
    • 34.10.5 TWI Clock Waveform Generator Register
    • 34.10.6 TWI Status Register
    • 34.10.7 TWI Interrupt Enable Register
    • 34.10.8 TWI Interrupt Disable Register
    • 34.10.9 TWI Interrupt Mask Register
    • 34.10.10 TWI Receive Holding Register
    • 34.10.11 TWI Transmit Holding Register
• 35. Universal Synchronous/Asynchronous Receiver/Transceiver
  • 35.1 Description
  • 35.2 Block Diagram
  • 35.3 Application Block Diagram
  • 35.4 I/O Lines Description
  • 35.5 Product Dependencies
    • 35.5.1 I/O Lines
    • 35.5.2 Power Management
    • 35.5.3 Interrupt
  • 35.6 Functional Description
    • 35.6.1 Baud Rate Generator
    • 35.6.2 Receiver and Transmitter Control
    • 35.6.3 Synchronous and Asynchronous Modes
    • 35.6.4 ISO7816 Mode
    • 35.6.5 IrDA Mode
    • 35.6.6 RS485 Mode
    • 35.6.7 Test Modes
  • 35.7 USART User Interface
    • 35.7.1 USART Control Register
    • 35.7.2 USART Mode Register
    • 35.7.3 USART Interrupt Enable Register
    • 35.7.4 USART Interrupt Disable Register
    • 35.7.5 USART Interrupt Mask Register
    • 35.7.6 USART Channel Status Register
    • 35.7.7 USART Receive Holding Register
    • 35.7.8 USART Transmit Holding Register
    • 35.7.9 USART Baud Rate Generator Register
    • 35.7.10 USART Receiver Time-out Register
    • 35.7.11 USART Transmitter Timeguard Register
    • 35.7.12 USART FI DI RATIO Register
    • 35.7.13 USART Number of Errors Register
    • 35.7.14 USART Manchester Configuration Register
    • 35.7.15 USART IrDA FILTER Register
• 36. Serial Synchronous Controller (SSC)
  • 36.1 Description
  • 36.2 Block Diagram
  • 36.3 Application Block Diagram
  • 36.4 Pin Name List
  • 36.5 Product Dependencies
    • 36.5.1 I/O Lines
    • 36.5.2 Power Management
    • 36.5.3 Interrupt
  • 36.6 Functional Description
    • 36.6.1 Clock Management
    • 36.6.2 Transmitter Operations
    • 36.6.3 Receiver Operations
    • 36.6.4 Start
    • 36.6.5 Frame Sync
    • 36.6.6 Receive Compare Modes
    • 36.6.7 Data Format
    • 36.6.8 Loop Mode
    • 36.6.9 Interrupt
  • 36.7 SSC Application Examples
  • 36.8 Synchronous Serial Controller (SSC) User Interface
    • 36.8.1 SSC Control Register
    • 36.8.2 SSC Clock Mode Register
    • 36.8.3 SSC Receive Clock Mode Register
    • 36.8.4 SSC Receive Frame Mode Register
    • 36.8.5 SSC Transmit Clock Mode Register
    • 36.8.6 SSC Transmit Frame Mode Register
    • 36.8.7 SSC Receive Holding Register
    • 36.8.8 SSC Transmit Holding Register
    • 36.8.9 SSC Receive Synchronization Holding Register
    • 36.8.10 SSC Transmit Synchronization Holding Register
    • 36.8.11 SSC Receive Compare 0 Register
    • 36.8.12 SSC Receive Compare 1 Register
    • 36.8.13 SSC Status Register
    • 36.8.14 SSC Interrupt Enable Register
    • 36.8.15 SSC Interrupt Disable Register
    • 36.8.16 SSC Interrupt Mask Register
• 37. AC’97 Controller (AC’97C)
  • 37.1 Description
  • 37.2 Block Diagram
  • 37.3 Pin Name List
  • 37.4 Application Block Diagram
  • 37.5 Product Dependencies
    • 37.5.1 I/O Lines
    • 37.5.2 Power Management
    • 37.5.3 Interrupt
  • 37.6 Functional Description
    • 37.6.1 Protocol overview
    • 37.6.2 AC‘97 Controller Channel Organization
    • 37.6.3 Variable Sample Rate
    • 37.6.4 Power Management
  • 37.7 AC’97 Controller (AC97C) User Interface
    • 37.7.1 AC’97 Controller Mode Register
    • 37.7.2 AC’97 Controller Input Channel Assignment Register
    • 37.7.3 AC’97 Controller Output Channel Assignment Register
    • 37.7.4 AC’97 Controller Codec Channel Receive Holding Register
    • 37.7.5 AC’97 Controller Codec Channel Transmit Holding Register
    • 37.7.6 AC’97 Controller Channel A, Channel B, Channel C Receive Holding Register
    • 37.7.7 AC’97 Controller Channel A, Channel B, Channel C Transmit Holding Register
    • 37.7.8 AC’97 Controller Channel A Status Register
    • 37.7.9 AC’97 Controller Channel B Status Register
    • 37.7.10 AC’97 Controller Channel C Status Register
    • 37.7.11 AC’97 Controller Codec Channel Status Register
    • 37.7.12 AC’97 Controller Channel A Mode Register
    • 37.7.13 AC’97 Controller Channel B Mode Register
    • 37.7.14 AC’97 Controller Channel C Mode Register
    • 37.7.15 AC’97 Controller Codec Channel Mode Register
    • 37.7.16 AC’97 Controller Status Register
    • 37.7.17 AC’97 Controller Interrupt Enable Register
    • 37.7.18 AC’97 Controller Interrupt Disable Register
    • 37.7.19 AC’97 Controller Interrupt Mask Register
• 38. Timer Counter (TC)
  • 38.1 Description
  • 38.2 Block Diagram
  • 38.3 Pin Name List
  • 38.4 Product Dependencies
    • 38.4.1 I/O Lines
    • 38.4.2 Power Management
    • 38.4.3 Interrupt
  • 38.5 Functional Description
    • 38.5.1 TC Description
    • 38.5.2 16-bit Counter
    • 38.5.3 Clock Selection
    • 38.5.4 Clock Control
    • 38.5.5 TC Operating Modes
    • 38.5.6 Trigger
    • 38.5.7 Capture Operating Mode
    • 38.5.8 Capture Registers A and B
    • 38.5.9 Trigger Conditions
    • 38.5.10 Waveform Operating Mode
    • 38.5.11 Waveform Selection
    • 38.5.12 External Event/Trigger Conditions
    • 38.5.13 Output Controller
  • 38.6 Timer Counter (TC) User Interface
    • 38.6.1 TC Block Control Register
    • 38.6.2 TC Block Mode Register
    • 38.6.3 TC Channel Control Register
    • 38.6.4 TC Channel Mode Register: Capture Mode
    • 38.6.5 TC Channel Mode Register: Waveform Mode
    • 38.6.6 TC Counter Value Register
    • 38.6.7 TC Register A
    • 38.6.8 TC Register B
    • 38.6.9 TC Register C
    • 38.6.10 TC Status Register
    • 38.6.11 TC Interrupt Enable Register
    • 38.6.12 TC Interrupt Disable Register
    • 38.6.13 TC Interrupt Mask Register
• 39. Controller Area Network (CAN)
  • 39.1 Description
  • 39.2 Block Diagram
  • 39.3 Application Block Diagram
  • 39.4 I/O Lines Description
  • 39.5 Product Dependencies
    • 39.5.1 I/O Lines
    • 39.5.2 Power Management
    • 39.5.3 Interrupt
  • 39.6 CAN Controller Features
    • 39.6.1 CAN Protocol Overview
    • 39.6.2 Mailbox Organization
    • 39.6.3 Time Management Unit
    • 39.6.4 CAN 2.0 Standard Features
    • 39.6.5 Low-power Mode
  • 39.7 Functional Description
    • 39.7.1 CAN Controller Initialization
    • 39.7.2 CAN Controller Interrupt Handling
    • 39.7.3 CAN Controller Message Handling
    • 39.7.4 CAN Controller Timing Modes
  • 39.8 Controller Area Network (CAN) User Interface
    • 39.8.1 CAN Mode Register
    • 39.8.2 CAN Interrupt Enable Register
    • 39.8.3 CAN Interrupt Disable Register
    • 39.8.4 CAN Interrupt Mask Register
    • 39.8.5 CAN Status Register
    • 39.8.6 CAN Baudrate Register
    • 39.8.7 CAN Timer Register
    • 39.8.8 CAN Timestamp Register
    • 39.8.9 CAN Error Counter Register
    • 39.8.10 CAN Transfer Command Register
    • 39.8.11 CAN Abort Command Register
    • 39.8.12 CAN Message Mode Register
    • 39.8.13 CAN Message Acceptance Mask Register
    • 39.8.14 CAN Message ID Register
    • 39.8.15 CAN Message Family ID Register
    • 39.8.16 CAN Message Status Register
    • 39.8.17 CAN Message Data Low Register
    • 39.8.18 CAN Message Data High Register
    • 39.8.19 CAN Message Control Register
• 40. Pulse Width Modulation (PWM) Controller
  • 40.1 Description
  • 40.2 Block Diagram
  • 40.3 I/O Lines Description
  • 40.4 Product Dependencies
    • 40.4.1 I/O Lines
    • 40.4.2 Power Management
    • 40.4.3 Interrupt Sources
  • 40.5 Functional Description
    • 40.5.1 PWM Clock Generator
    • 40.5.2 PWM Channel
    • 40.5.3 PWM Controller Operations
  • 40.6 Pulse Width Modulation (PWM) Controller User Interface
    • 40.6.1 PWM Mode Register
    • 40.6.2 PWM Enable Register
    • 40.6.3 PWM Disable Register
    • 40.6.4 PWM Status Register
    • 40.6.5 PWM Interrupt Enable Register
    • 40.6.6 PWM Interrupt Disable Register
    • 40.6.7 PWM Interrupt Mask Register
    • 40.6.8 PWM Interrupt Status Register
    • 40.6.9 PWM Channel Mode Register
    • 40.6.10 PWM Channel Duty Cycle Register
    • 40.6.11 PWM Channel Period Register
    • 40.6.12 PWM Channel Counter Register
    • 40.6.13 PWM Channel Update Register
• 41. MultiMedia Card Interface (MCI)
  • 41.1 Description
  • 41.2 Block Diagram
  • 41.3 Application Block Diagram
  • 41.4 Pin Name List
  • 41.5 Product Dependencies
    • 41.5.1 I/O Lines
    • 41.5.2 Power Management
    • 41.5.3 Interrupt
  • 41.6 Bus Topology
  • 41.7 MultiMedia Card Operations
    • 41.7.1 Command - Response Operation
  • 41.8
    • 41.8.1 Data Transfer Operation
    • 41.8.2 Read Operation
    • 41.8.3 Write Operation
  • 41.9 SD/SDIO Card Operations
    • 41.9.1 SDIO Data Transfer Type
    • 41.9.2 SDIO Interrupts
  • 41.10 MultiMedia Card Interface (MCI) User Interface
    • 41.10.1 MCI Control Register
    • 41.10.2 MCI Mode Register
    • 41.10.3 MCI Data Timeout Register
    • 41.10.4 MCI SDCard/SDIO Register
    • 41.10.5 MCI Argument Register
    • 41.10.6 MCI Command Register
    • 41.10.7 MCI Block Register
    • 41.10.8 MCI Response Register
    • 41.10.9 MCI Receive Data Register
    • 41.10.10 MCI Transmit Data Register
    • 41.10.11 MCI Status Register
    • 41.10.12 MCI Interrupt Enable Register
    • 41.10.13 MCI Interrupt Disable Register
    • 41.10.14 MCI Interrupt Mask Register
• 42. 10/100 Ethernet MAC (EMAC)
  • 42.1 Description
  • 42.2 Block Diagram
  • 42.3 Functional Description
    • 42.3.1 Memory Interface
    • 42.3.2 Transmit Block
    • 42.3.3 Pause Frame Support
    • 42.3.4 Receive Block
    • 42.3.5 Address Checking Block
    • 42.3.6 Broadcast Address
    • 42.3.7 Hash Addressing
    • 42.3.8 Copy All Frames (or Promiscuous Mode)
    • 42.3.9 Type ID Checking
    • 42.3.10 VLAN Support
    • 42.3.11 PHY Maintenance
    • 42.3.12 Media Independent Interface
  • 42.4 Programming Interface
    • 42.4.1 Initialization
  • 42.5 10/100 Ethernet MAC (EMAC) User Interface
    • 42.5.1 Network Control Register
    • 42.5.2 Network Configuration Register
    • 42.5.3 Network Status Register
    • 42.5.4 Transmit Status Register
    • 42.5.5 Receive Buffer Queue Pointer Register
    • 42.5.6 Transmit Buffer Queue Pointer Register
    • 42.5.7 Receive Status Register
    • 42.5.8 Interrupt Status Register
    • 42.5.9 Interrupt Enable Register
    • 42.5.10 Interrupt Disable Register
    • 42.5.11 Interrupt Mask Register
    • 42.5.12 PHY Maintenance Register
    • 42.5.13 Pause Time Register
    • 42.5.14 Hash Register Bottom
    • 42.5.15 Hash Register Top
    • 42.5.16 Specific Address 1 Bottom Register
    • 42.5.17 Specific Address 1 Top Register
    • 42.5.18 Specific Address 2 Bottom Register
    • 42.5.19 Specific Address 2 Top Register
    • 42.5.20 Specific Address 3 Bottom Register
    • 42.5.21 Specific Address 3 Top Register
    • 42.5.22 Specific Address 4 Bottom Register
    • 42.5.23 Specific Address 4 Top Register
    • 42.5.24 Type ID Checking Register
    • 42.5.25 User Input/Output Register
    • 42.5.26 EMAC Statistic Registers
• 43. USB Host Port (UHP)
  • 43.1 Description
  • 43.2 Block Diagram
  • 43.3 Product Dependencies
    • 43.3.1 I/O Lines
    • 43.3.2 Power Management
    • 43.3.3 Interrupt
  • 43.4 Functional Description
    • 43.4.1 Host Controller Interface
    • 43.4.2 Host Controller Driver
  • 43.5 Typical Connection
• 44. USB High Speed Device Port (UDPHS)
  • 44.1 Description
  • 44.2 Block Diagram
  • 44.3 Typical Connection
  • 44.4 Functional Description
    • 44.4.1 USB V2.0 High Speed Device Port Introduction
    • 44.4.2 USB V2.0 High Speed Transfer Types
    • 44.4.3 USB Transfer Event Definitions
    • 44.4.4 USB V2.0 High Speed BUS Transactions
    • 44.4.5 Endpoint Configuration
    • 44.4.6 Transfer With DMA
    • 44.4.7 Transfer Without DMA
    • 44.4.8 Handling Transactions with USB V2.0 Device Peripheral
    • 44.4.9 Speed Identification
    • 44.4.10 USB V2.0 High Speed Global Interrupt
    • 44.4.11 Endpoint Interrupts
    • 44.4.12 Power Modes
    • 44.4.13 Test Mode
  • 44.5 USB High Speed Device Port (UDPHS) User Interface
    • 44.5.1 UDPHS Control Register
    • 44.5.2 UDPHS Frame Number Register
    • 44.5.3 UDPHS Interrupt Enable Register
    • 44.5.4 UDPHS Interrupt Status Register
    • 44.5.5 UDPHS Clear Interrupt Register
    • 44.5.6 UDPHS Endpoints Reset Register
    • 44.5.7 UDPHS Test Register
    • 44.5.8 UDPHS Endpoint Configuration Register
    • 44.5.9 UDPHS Endpoint Control Enable Register
    • 44.5.10 UDPHS Endpoint Control Disable Register
    • 44.5.11 UDPHS Endpoint Control Register
    • 44.5.12 UDPHS Endpoint Set Status Register
    • 44.5.13 UDPHS Endpoint Clear Status Register
    • 44.5.14 UDPHS Endpoint Status Register
    • 44.5.15 UDPHS DMA Channel Transfer Descriptor
    • 44.5.16 UDPHS DMA Next Descriptor Address Register
    • 44.5.17 UDPHS DMA Channel Address Register
    • 44.5.18 UDPHS DMA Channel Control Register
    • 44.5.19 UDPHS DMA Channel Status Register
• 45. Image Sensor Interface (ISI)
  • 45.1 Overview
  • 45.2 Block Diagram
  • 45.3 Functional Description
    • 45.3.1 Data Timing
    • 45.3.2 Data Ordering
    • 45.3.3 Clocks
    • 45.3.4 Preview Path
    • 45.3.5 Codec Path
  • 45.4 Image Sensor Interface (ISI) User Interface
    • 45.4.1 ISI Control 1 Register
    • 45.4.2 ISI Control 2 Register
    • 45.4.3 ISI Status Register
    • 45.4.4 Interrupt Enable Register
    • 45.4.5 ISI Interrupt Disable Register
    • 45.4.6 ISI Interrupt Mask Register
    • 45.4.7 ISI Preview Register
    • 45.4.8 ISI Preview Decimation Factor Register
    • 45.4.9 ISI Preview Primary FBD Register
    • 45.4.10 ISI Codec DMA Base Address Register
    • 45.4.11 ISI Color Space Conversion YCrCb to RGB Set 0 Register
    • 45.4.12 ISI Color Space Conversion YCrCb to RGB Set 1 Register
    • 45.4.13 ISI Color Space Conversion RGB to YCrCb Set 0 Register
    • 45.4.14 ISI Color Space Conversion RGB to YCrCb Set 1 Register
    • 45.4.15 ISI Color Space Conversion RGB to YCrCb Set 2 Register
• 46. Analog-to-Digital Converter (ADC)
  • 46.1 Description
  • 46.2 Block Diagram
  • 46.3 Signal Description
  • 46.4 Product Dependencies
    • 46.4.1 Power Management
    • 46.4.2 Interrupt Sources
    • 46.4.3 Analog Inputs
    • 46.4.4 I/O Lines
    • 46.4.5 Timer Triggers
    • 46.4.6 Conversion Performances
  • 46.5 Functional Description
    • 46.5.1 Analog-to-digital Conversion
    • 46.5.2 Conversion Reference
    • 46.5.3 Conversion Resolution
    • 46.5.4 Conversion Results
    • 46.5.5 Conversion Triggers
    • 46.5.6 Sleep Mode and Conversion Sequencer
    • 46.5.7 ADC Timings
  • 46.6 Analog-to-digital Converter (ADC) User Interface
    • 46.6.1 ADC Control Register
    • 46.6.2 ADC Mode Register
    • 46.6.3 ADC Channel Enable Register
    • 46.6.4 ADC Channel Disable Register
    • 46.6.5 ADC Channel Status Register
    • 46.6.6 ADC Status Register
    • 46.6.7 ADC Last Converted Data Register
    • 46.6.8 ADC Interrupt Enable Register
    • 46.6.9 ADC Interrupt Disable Register
    • 46.6.10 ADC Interrupt Mask Register
    • 46.6.11 ADC Channel Data Register
• 47. AT91CAP9 Electrical Characteristics
  • 47.1 Absolute Maximum Ratings
  • 47.2 DC Characteristics
  • 47.3 Power Consumption
    • 47.3.1 Power Consumption versus Modes
  • 47.4 32 kHz Crystal Oscillator Characteristics
  • 47.5 12 MHz Main Oscillator Characteristics
  • 47.6 PLLA and PLLB Characteristics
  • 47.7 UTMI PLL Characteristics
  • 47.8 USB HS Characteristics
    • 47.8.1 Electrical Characteristics
    • 47.8.2 Static Power Consumption
    • 47.8.3 Dynamic Power Consumption
  • 47.9 ADC
  • 47.10 Timings
    • 47.10.1 Corner Definition
    • 47.10.2 Processor Clock
    • 47.10.3 Maximum Speed of the I/Os
    • 47.10.4 SMC Timings
    • 47.10.5 SDRAMC Timings
    • 47.10.6 DDR SDRAMC Timings
    • 47.10.7 SPI
    • 47.10.8 ISI Timings
    • 47.10.9 MCI Timings
    • 47.10.10 UDP Timings
    • 47.10.11 EMAC Timings
    • 47.10.12 AC97 Timings
• 48. AT91CAP9 Mechanical Characteristics
  • 48.1 Thermal Considerations
    • 48.1.1 Thermal Data
    • 48.1.2 Junction Temperature
  • 48.2 Package Drawing
  • 48.3 Soldering Profile
• 49. AT91CAP9 Ordering Information
• 50. AT91CAP9 Errata
  • 50.1 Marking
  • 50.2 Errata
• 51. Revision History
• Table of Contents