Freescale Semiconductor MCF5480 - Manual (Page 111)

Programming Model
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 3-7
• The ASID is optionally included in the specification of the hardware breakpoint registers. As an
example, the four PC breakpoint registers are each expanded by 8 bits, so that a specific ASID
value may be programmed as part of the breakpoint instruction address. Likewise, each operand
address/data breakpoint register is expanded to include an ASID value. Finally, new control
registers define if and how the ASID is to be included in the breakpoint comparison trigger logic.
• The debug module implements the concept of ownership trace in which the ASID value may be
optionally displayed as part of the real-time trace functionality. When enabled, real-time trace
displays instruction addresses on every change-of-flow instruction that is not absolute or
PC-relative. For Revision D, this instruction address display optionally includes the contents of the
ASID, thus providing the complete instruction virtual address on these instructions.
Additionally when a Sync_PC serial BDM command is loaded from the external development
system, the processor optionally displays the complete virtual instruction address, including the
8-bit ASID value.
In addition to these ASID-related changes, the new MMU control registers are accessible by using serial
BDM commands. The same BDM access capabilities are also provided for the EMAC and FPU
programming models.
Finally, a new serial BDM command is implemented to assist debugging when a software error generates
an incorrect memory address that hangs the external bus. The new BDM command attempts to break this
condition by forcing a bus termination.
3.3 Programming Model
The MCF548x programming model consists of two instruction and register groups—user and supervisor,
shown in Figure 3-3 . User mode programs are restricted to user, EMAC, and floating point instructions
and programming models. Supervisor-mode system software can reference all user-mode, EMAC, and
floating point instructions and registers and additional supervisor instructions and control registers. The
user or supervisor programming model is selected based on SR[S]. The following sections describe the
registers in the user, EMAC, floating point, and supervisor programming models.