Freescale Semiconductor MCF5480 - Manual (Page 169)

Virtual Memory Management Architecture
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 5-3
Figure 5-1. CF4e Processor Core Block with MMU
5.2.3 MMU Architecture Implementation
This section describes ColdFire design additions and changes for the MMU architecture. It includes
precise faults, MMU access, virtual mode, virtual memory references, instruction and data cache
addresses, supervisor/user stack pointers, access error stack frame additions, expanded control register
space, ACR address improvements, supervisor protection, and debugging in a virtual environment.
PSTDDATA PSTCLK
Instruction Fetch
IAG
IC1
Branch
Cache
IC2
IED
Branch
Accel.
IB
Operand Execution Pipeline
DS
OAG
OC1
OC2
EX
DA
K2M
M Bus
J
KC1
KC2
BDM DDATA
DSCLK DSI DSDO
J
KC1
KC2
Instruction
Memory
Data
Memory
FPU EMAC
Memory
Management
Physical
KC1
Physical
KC1
Unit
(MMU)
DS
Pipeline
Misalignment
Module