Freescale Semiconductor MCF5480 - Manual (Page 170)

MCF548x Reference Manual, Rev. 3
5-4 Freescale Semiconductor
5.2.3.1 Precise Faults
The MMU architecture performs virtual-to-physical address translation and permission checking in the
core. To support demand-paging, the core design provides a precise, recoverable fault for all references.
5.2.3.2 MMU Access
The MMU TLB control registers are memory-mapped. The TLB entries are read and written indirectly
through the MMU control registers. The memory space for these resources is defined by a new supervisor
program model register, the MMU base address register (MMUBAR). This register defines a
supervisor-mode, data-only space. It has the highest priority for the data address mode determination.
5.2.3.3 Virtual Mode
Every instruction and data reference is either a virtual or physical address mode access. All addresses for
special mode (interrupt acknowledges, emulator mode operations, etc.) accesses are physical. All
addresses are physical if the MMU is not enabled. If the MMU is present and enabled, the address mode
for normal accesses is determined by the MMUBAR, RAMBARs, and ACRs in the priority order listed.
Addresses that hit in the MMUBAR, RAMBARs, and ACRs are treated as physical references. These
addresses are not translated and their address attributes are sourced from the highest priority mapping
register they hit. If an address hits none of these mapping registers, it is a virtual address and is sent to the
MMU. If the MMU is enabled, the default CACR information is not used.
5.2.3.4 Virtual Memory References
The ColdFire MMU architecture references the MMU for all virtual mode accesses to the . MMU, SRAM
and ACR memory spaces are treated as physical address spaces and all permissions that apply to these
spaces are contained in the respective mapping register. The virtual mode access either hits or misses in
the TLB of the MMU. A TLB miss generates an access fault in the processor, allowing software to either
load the appropriate translation into the TLB and restart the faulting instruction or abort the process. Each
TLB hit checks permissions based on the access control information in the referenced TLB entry.
5.2.3.5 Instruction and Data Cache Addresses
For a given page size, virtual address bits that reference within a page are called the in-page address. All
bits above this are the virtual page number. Likewise, the physical address has a physical page number and
in-page address bits. Virtual and physical in-page address bits are the same; the MMU translates the virtual
page number to the physical page number.
Instruction and data caches are accessed with the untranslated address. The translated address is used for
cache allocation. That is, caches are virtual-address accessed and physical-address tagged. If instruction
and data cache addresses are not larger than the in-page address for the smallest active MMU page, the
cache is considered physically accessed; if they are larger, the cache can have aliasing problems between
virtual and cache addresses. Software handles these problems by forcing the virtual address to be equal to
the physical address for those bits addressing the cache, but above the in-page address of the smallest
active page size. The number of these bits depends on cache and page sizes.
Caches are addressed with the virtual address, because the cache uses synchronous memory elements, and
an access starts at the rising-clock edge of the first pipeline stage. The MMU provides a physical address
midway through this cycle.
If the cache set address has fewer bits than the in-page address, the cache is considered physically
addressed because these bits are the same in the virtual and physical addresses. If the cache set address has