Freescale Semiconductor MCF5480 - Manual (Page 175)

MMU Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 5-9
5.5 MMU Definition
The ColdFire MMU provides a virtual address, demand-paged memory architecture. The MMU supports
hardware address translation acceleration using software-managed TLBs. It enforces permission checking
on a per-memory request basis, and has control, status, and fault registers for MMU operation.
5.5.1 Effective Address Attribute Determination
The ColdFire core generates an effective memory address for all instruction fetches and data read and write
memory accesses. The previous ColdFire memory access control model was based strictly on physical
addresses. Every memory request address is a physical address that is analyzed by this memory access
control logic and assigned address attributes, which include the following:
• Cache mode
• SRAM enable information
• Write protect information
• Write mode information
These attributes control processing of the memory request. The address itself is not affected by memory
access control logic.
Instruction and data references base effective address attributes and access mode on the instruction type
and the effective address. Accesses are of the following two types:
• Special mode accesses, including interrupt acknowledges, reads/writes to program-visible control
registers (such as CACR, ROMBARs, RAMBARs, and ACRs), cache control commands
(CPUSHL and INTOUCH), and emulator mode operations. These accesses have the following
attributes:
— Non-cacheable
— Precise
— No write protection
Unless the CPU space/IACK mask bit is set, interrupt acknowledge cycles and emulator mode
operations are allowed to hit in RAMBARs and ROMBARs. All other operations are normal mode
accesses.
• Normal mode accesses. For these accesses, an effective cache mode, precision and write-protection
are calculated for each request.
For data, a normal mode access address is compared with the following priority, from highest to lowest:
RAMBAR0, RAMBAR1, ROMBAR0, ROMBAR1, ACR0, and ACR1. If no match is found, default
attributes in the CACR are used. The priority for instruction accesses is RAMBAR0, RAMBAR1,
ROMBAR0, ROMBAR1, ACR2, and ACR3. Again, if no match is found, default CACR attributes are
used.
Only the test-and-set (TAS) instruction can generate a normal mode access with implied cache mode and
precision. TAS is a special, byte-sized, read-modify-write instruction used in synchronization routines. A
TAS data access that does not hit in the RAMBARs is non-cacheable and precise. TAS uses the normal
effective write protection.
The ColdFire MMU is an optional enhancement to the memory access control. If the MMU is present and
enabled, it adds two factors for calculating effective address attributes:
• MMUBAR defines a memory-mapped, privileged data-only space with the highest priority in
effective address attribute calculation for the data (that is, the MMUBAR has priority over
RAMBAR0).