5 mmu status register (mmusr), Mmu status register (mmusr) -14 – Freescale Semiconductor MCF5480 User Manual
Page 180
MCF548x Reference Manual, Rev. 3
5-14
Freescale Semiconductor
5.5.3.5
MMU Status Register (MMUSR)
MMUSR,
, is updated on all data access faults and search TLB operations.
5
CAS
Clear all non-locked TLB entries that match ASID. CAS is always reads as a zero.
0 No operation
1 Clear all non-locked TLB entries that match ASID register.
4
ITLB
ITLB operation. Used by TLB search and access operations that use the TLB allocation
address.
0 The MMU uses the DTLB to search or update the allocation address.
1 The MMU uses the ITLB for searches and updates of the allocation address.
3
ADR
TLB address select. Indicates which address to use when accessing the TLB.
0 Use the TLB allocation address for the TLB address.
1 Use MMUAR for the TLB address.
2
R/W
TLB access read/write select. Indicates whether to do a read or a write when accessing
the TLB.
0 Write
1 Read
1
ACC
MMU TLB access. This bit always reads as a zero. STLB is used for search operations.
0 No operation. ACC should be a zero to search the TLB.
1 The MMU reads or writes the TLB depending on R/W. For TLB reads, TLB tag and data
results are loaded into MMUTR and MMUDR. For TLB writes, the contents of these
registers are written to the TLB. The TLB is accessed using the TLB allocation address
if ADR is zero or using MMUAR if ADR is set.
0
UAA
Update allocation address. UAA always reads as a zero.
0 No operation
1 MMU updates the allocation address field with the MMU’s choice for the allocation
address in the ITLB or DTLB depending on the ITLB instruction operation bit.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
SPF
RF
WF
0
HIT
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MMUBAR + 0x008
Figure 5-6. MMU Status Register (MMUSR)
Table 5-6. MMUOR Field Descriptions (Continued)
Bits
Name
Description