Freescale Semiconductor MCF5480 - Manual (Page 184)

MCF548x Reference Manual, Rev. 3
5-18 Freescale Semiconductor
5.5.4 MMU TLB
Each TLB entry consists of two 32-bit fields. The first is the TLB tag entry, and the second is the TLB data
entry. TLB size and organization are implementation dependent. TLB entries can be read and written
through MMU registers. TLB contents are unaffected by reset.
7–6 CM Cache mode. If a Harvard TLB implementation is used, CM0 is a don’t care for the ITLB.
CM is ignored on writes and always reads as zero for the ITLB.
Instruction cache modes:
1x Page is non-cacheable.
0x Page is cacheable.
Data cache modes
00 Page is cacheable writethrough.
01 Page is cacheable copyback.
10 Page is non-cacheable precise.
11 Page is non-cacheable imprecise.
5 SP Supervisor protect. Controls user mode access to the page mapped by this entry.
0 Entry is not supervisor protected.
1 Entry is supervisor protected. An attempted user mode access that matches this entry
generates an access error exception.
4 R Read access enable. Indicates if data read accesses to this entry are allowed. If a Harvard
TLB implementation is used, this bit is a don’t care for the ITLB. This bit is ignored on writes
and always reads as zero for the ITLB.
0 Do not allow data read accesses. Attempted data read accesses that match this entry
generate an access error exception.
1 Allow data read accesses.
3 W Write access enable. Indicates if data write accesses are allowed to this entry. If separate
ITLB and DTLBs) are used, W is a don’t care for the ITLB. W is ignored on writes and reads
as zero for the ITLB.
0 Do not allow data write accesses. Attempted data write accesses that match this entry
generate an access error exception.
1 Allow data write accesses.
2 X Execute access enable. Indicates if instruction fetches to this entry are allowed. If separate
ITLB and DTLBs are is used, X is a don’t care for the DTLB. X is ignored on writes and
reads as zero for the DTLB.
0 Do not allow instruction fetches. Attempted instruction fetches that match this entry
cause an access error exception.
1 Allow instruction fetch accesses.
1 LK Lock entry bit. Indicates if this entry is included in the replacement algorithm. TLB hits of
locked entries do not update replacement algorithm information.
0 Include this entry when determining the best entry for a TLB allocation.
1 Do not allow this entry to be selected by the replacement algorithm.
0 — Reserved, should be cleared. Writes are ignored and reads return zeros.
Table 5-10. MMUDR Field Descriptions (Continued)
Bits Name Descriptions