Freescale Semiconductor MCF5480 - Manual (Page 188)

MCF548x Reference Manual, Rev. 3
5-22 Freescale Semiconductor
Binary state bits are updated on all TLB write (load) operations, as well as normal ITLB and DTLB hits
of non-locked entries. Also, if all entries in a binary state are locked, than that state is always set. That is,
if entries 15, 14, 13, and 12 were locked, LRU state bit rdRecent15To14 is forced to one.
For a completely valid TLB, binary state information determines the LRU entry. The CF4e replacement
algorithm is deterministic and, for the case of a full TLB (with no locked entries and always touching new
pages), the replacement entry repeats every 32 TLB loads.
5.6.3 TLB Locked Entries
Figure 5-11 is a ColdFire MMU Harvard TLB block diagram.
For TLB miss faults, the instruction restart model completely reexecutes an instruction on returning from
the exception handler. An instruction can touch two instruction pages (a 32- or 48-bit instruction can
straddle two pages) or four data pages (a memory-to-memory word or longword move where misaligned
source and destination operands straddle two pages). Therefore, one instruction may take two ITLB misses
and allocate two ITLB pages before completion. Likewise, one instruction may require four DTLB misses
and allocate four DTLB pages. Because of this, a pool of unlocked TLB entries must be available if virtual
memory is used.
The above examples show the fewest entries needed to guarantee an instruction can complete execution.
For good MMU performance, more unlocked TLB entries should be available.
rdRecent27 A one indicates 27 is more recent than 26
rdRecent25 A one indicates 25 is more recent than 24
rdRecent23 A one indicates 23 is more recent than 22
rdRecent21 A one indicates 21 is more recent than 20
rdRecent19 A one indicates 19 is more recent than 18
rdRecent17 A one indicates 17 is more recent than 16
rdRecent15 A one indicates 15 is more recent than 14
rdRecent13 A one indicates 13 is more recent than 12
rdRecent11 A one indicates 11 is more recent than 10
rdRecent09 A one indicates 09 is more recent than 08
rdRecent07 A one indicates 07 is more recent than 06
rdRecent05 A one indicates 05 is more recent than 04
rdRecent03 A one indicates 03 is more recent than 02
rdRecent01 A one indicates 01 is more recent than 00
Table 5-13. PLRU State Bits (Continued)
State Bits Meaning