Freescale Semiconductor MCF5480 - Manual (Page 205)

Floating-Point Post-Processing
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 6-15
rounding precision and mode. After rounding, the inexact bit (INEX) is set as described in Figure 6-12 .
Lastly, the magnitude of the result is checked to see if it exceeds the current rounding precision. If so, the
overflow (OVFL) bit is set, and a correctly signed infinity or correctly signed largest normalized number
is returned, depending on the rounding mode.
NOTE
INEX can also be set by OVFL, UNFL, and when denormalized numbers
are encountered.
6.5.2 Conditional Testing
Unlike operation-dependent integer condition codes, an instruction either always sets FPCC bits in the
same way or does not change them at all. Therefore, instruction descriptions do not include FPCC settings.
This section describes how FPCC bits are set.
FPCC bits differ slightly from integer condition codes. An FPU operation’s final result sets or clears FPCC
bits accordingly, independent of the operation itself. Integer condition code bits N and Z have this
characteristic, but V and C are set differently for different instructions. Table 6-8 lists FPCC settings for
each data type. Loading FPCC with another combination and executing a conditional instruction can
produce an unexpected branch condition.
The inclusion of the NAN data type in the IEEE floating-point number system requires each conditional
test to include FPCC[NAN] in its boolean equation. Because it cannot be determined whether a NAN is
bigger or smaller than an in-range number (since it is unordered), the compare instruction sets
FPCC[NAN] when an unordered compare is attempted. All arithmetic instructions that result in a NAN
also set the NAN bit. Conditional instructions interpret NAN being set as the unordered condition.
The IEEE-754 standard defines the following four conditions:
• Equal to (EQ)
• Greater than (GT)
• Less than (LT)
• Unordered (UN)
The standard requires only the generation of the condition codes as a result of a floating-point compare
operation. The FPU can test for these conditions and 28 others at the end of any operation affecting
condition codes. For floating-point conditional branch instructions, the processor logically combines the
4 bits of the FPCC condition codes to form 32 conditional tests, 16 of which cause an exception if an
Table 6-8. FPCC Encodings
Data Type N Z I NAN
+ Normalized or Denormalized 0 0 0 0
– Normalized or Denormalized 1 0 0 0
+ 0 0 1 0 0
– 0 1 1 0 0
+ Infinity 0 0 1 0
– Infinity 1 0 1 0
+ NAN 0 0 0 1
– NAN 1 0 0 1