Freescale Semiconductor MCF5480 - Manual (Page 224)

MCF548x Reference Manual, Rev. 3
7-4 Freescale Semiconductor
The mapping of a given access into the SRAM uses the following algorithm to determine if the access hits
in the memory:
if (RAMBAR[0] = 1)
if (((access = instructionFetch) & (RAMBAR[7] = 1)) |
((access = dataReference) & (RAMBAR[7] = 0)))
if (requested address[31:10] = RAMBAR[31:10])
if (requested address[31:n] = RAMBAR[31:n]
if (ASn of the requested type = 0)
Access is mapped to the SRAM module
if (access = read)
Read the SRAM and return the data
if (access = write)
if (RAMBAR[8] = 0)
Write the data into the SRAM
else Signal a write-protect access error
ASn refers to the five address space mask bits: C/I, SC, SD, UC, and UD.
7.5 SRAM Initialization
After a hardware reset, the contents of each SRAM module are undefined. The valid bits, RAMBARn[V],
are cleared, disabling the SRAM modules. If the SRAM requires initialization with instructions or data,
the following steps should be performed:
1. Load RAMBARn with bit 7 = 0, mapping the SRAM module to the desired location. Clearing
RAMBARn[7] logically connects the SRAM module to the processor’s data bus.
2. Read the source data and write it to the SRAM. Various instructions support this function,
including memory-to-memory move instructions and the move multiple instruction (MOVEM).
MOVEM is optimized to generate line-sized burst fetches on line-aligned addresses, so it
generally provides maximum performance.
5 C/I Address space masks (ASn). These fields allow certain types of accesses to be masked,
or inhibited from accessing the SRAM module. These bits are useful for power
management as described in
Section 7.6, “Power Management .” In particular, C/I is
typically set.
The address space mask bits are follows:
C/I = CPU space/interrupt acknowledge cycle mask. Note that C/I must be set if BA = 0.
SC = Supervisor code address space mask
SD = Supervisor data address space mask
UC = User code address space mask
UD = User data address space mask
For each ASn bit:
0 An access to the SRAM module can occur for this address space
1 Disable this address space from the SRAM module. If a reference using this address
space is made, it is inhibited from accessing the SRAM module and is processed like
any other non-SRAM reference.
4 SC
3 SD
2 UC
1 UD
0 V Valid. Enables/disables the SRAM module. V is cleared at reset.
0 RAMBAR contents are not valid.
1 RAMBAR contents are valid.
Table 7-1. RAMBARn Field Description (Continued)
Bits Name Description