Freescale Semiconductor MCF5480 - Manual (Page 232)

MCF548x Reference Manual, Rev. 3
7-12 Freescale Semiconductor
Valid cache entries that match during cache-inhibited address accesses are neither pushed nor invalidated.
Such a scenario suggests that the associated cache mode for this address space was changed. To avoid this,
it is generally recommended to use the CPUSHL instruction to push or invalidate the cache entry or set
CACR[DCINVA] to invalidate the data cache before switching cache modes.
7.9.1 Caching Modes
For every memory reference generated by the processor or debug module, a set of effective attributes is
determined based on the address and the ACRs. Caching modes determine how the cache handles an
access. A data access can be cacheable in either write-through or copyback mode; it can be cache-inhibited
in precise or imprecise modes. For normal accesses, the ACRn[CM] bit corresponding to the address of
the access specifies the caching modes. If an address does not match an ACR, the default caching mode is
defined by CACR[DDCM,IDCM]. The specific algorithm is as follows:
if (address == ACR0-address including mask)
effective attributes = ACR0 attributes
else if (address == ACR1-address including mask)
effective attributes = ACR1 attributes
else effective attributes = CACR default attributes
Addresses matching an ACR can also be write-protected using ACR[W]. Addresses that do not match
either ACR can be write-protected using CACR[DW].
Reset disables the cache and clears all CACR bits. As shown in
Figure 7-4 , reset does not automatically
invalidate cache entries; they must be invalidated through software.
The ACRs allow the defaults selected in the CACR to be overridden. In addition, some instructions (for
example, CPUSHL) and processor core operations perform accesses that have an implicit caching mode
associated with them. The following sections discuss the different caching accesses and their associated
cache modes.
7.9.1.1 Cacheable Accesses
If ACRn[CM] or the default field of the CACR indicates write-through or copyback, the access is
cacheable. A read access to a write-through or copyback region is read from the cache if matching data is
found. Otherwise, the data is read from memory and the cache is updated. When a line is being read from
memory for either a write-through or copyback read miss, the longword within the line that contains the
core-requested data is loaded first and the requested data is given immediately to the processor, without
waiting for the three remaining longwords to reach the cache.
The following sections describe write-through and copyback modes in detail. Note that some of this
information applies to data caches only.
7.9.1.1.1 Write-Through Mode (Data Cache Only)
Write accesses to regions specified as write-through are always passed on to the external bus, although the
cycle can be buffered, depending on the state of CACR[DESB]. Writes in write-through mode are handled
with a no-write-allocate policy—that is, writes that miss in the cache are written to the external bus but do
not cause the corresponding line in memory to be loaded into the cache. Write accesses that hit always
write through to memory and update matching cache lines. The cache supplies data to data-read accesses
that hit in the cache; read misses cause a new cache line to be loaded into the cache.