Freescale Semiconductor MCF5480 - Manual (Page 233)

Cache Operation
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 7-13
7.9.1.1.2 Copyback Mode (Data Cache Only)
Copyback regions are typically used for local data structures or stacks to minimize external bus use and
reduce write-access latency. Write accesses to regions specified as copyback that hit in the cache update
the cache line and set the corresponding M bit without an external bus access.
The cache should be flushed using the CPUSHL instruction before invalidating the cache in copyback
mode using the CINV bit. Modified cache data is written to memory only if the line is replaced because of
a miss or a CPUSHL instruction pushes the line. If a byte, word, longword, or line write access misses in
the cache, the required cache line is read from memory, thereby updating the cache. When a miss selects
a modified cache line for replacement, the modified cache data moves to the push buffer. The replacement
line is read into the cache and the push buffer contents are then written to memory.
7.9.1.2 Cache-Inhibited Accesses
Memory regions can be designated as cache-inhibited, which is useful for memory containing targets such
as I/O devices and shared data structures in multiprocessing systems. It is also important to not cache the
MCF548x memory-mapped registers. If the corresponding ACRn[CM] or CACR[DDCM] indicates
cache-inhibited, precise or imprecise, the access is cache-inhibited. The caching operation is identical for
both cache-inhibited modes, which differ only regarding recovery from an external bus error.
In determining whether a memory location is cacheable or cache-inhibited, the CPU checks
memory-control registers in the following order:
1. RAMBARs
2. ACR0 and ACR2
3. ACR1 and ACR3
4. If an access does not hit in the RAMBARs or the ACRs, the default is provided for all accesses in
CACR.
Cache-inhibited write accesses bypass the cache, and a corresponding external write is performed.
Cache-inhibited reads bypass the cache and are performed on the external bus, except when all of the
following conditions are true:
• The cache-inhibited fill-buffer bit, CACR[DNFB], is set.
• The access is an instruction read.
• The access is normal (that is, TT = 0).
In this case, a fetched line is stored in the fill buffer and remains valid there; the cache can service
additional read accesses from this buffer until another fill occurs or a cache-invalidate-all operation occurs.
If ACRn[CM] indicates cache-inhibited mode, precise or imprecise, the controller bypasses the cache and
performs an external transfer. If a line in the cache matches the address and the mode is cache-inhibited,
the cache does not automatically push the line if it is modified, nor does it invalidate the line if it is valid.
Before switching cache mode, execute a CPUSHL instruction or set CACR[DCINVA,ICINVA] to
invalidate the entire cache.
If ACRn[CM] indicates precise mode, the sequence of read and write accesses to the region is guaranteed
to match the instruction sequence. In imprecise mode, the processor core allows read accesses that hit in
the cache to occur before completion of a pending write from a previous instruction. Writes are not
deferred past data-read accesses that miss the cache (that is, that must be read from the bus).
Precise operation forces data-read accesses for an instruction to occur only once by preventing the
instruction from being interrupted after data is fetched. Otherwise, if the processor is not in precise mode,