4 memory map/register definition, Memory map/register definition -9, Section 8.4 – Freescale Semiconductor MCF5480 User Manual
Page 259: Memory map/register definition
Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
8-9
8.4
Memory Map/Register Definition
In addition to the existing BDM commands that provide access to the processor’s registers and the memory
subsystem, the debug module contains 19 registers to support the required functionality. These registers
are also accessible from the processor’s supervisor programming model by executing the WDEBUG
instruction (write only). Thus, the breakpoint hardware in the debug module can be read or written by the
external development system using the debug serial interface
or written by the operating system running
on the processor core. Software is responsible for guaranteeing that accesses to these resources are
serialized and logically consistent. Hardware provides a locking mechanism in the CSR to allow the
external development system to disable any attempted writes by the processor to the breakpoint registers
(setting CSR[IPW]). BDM commands must not be issued if the WDEBUG instruction is used to access
debug module registers or the resulting behavior is undefined.
These registers, shown in
, are treated as 32-bit quantities, regardless of the number of
implemented bits.
Figure 8-5. Debug Programming Model
ABLR1
ABHR1
AATR1
PC breakpoint 1 register
PC breakpoint 3 register
PC breakpoint mask register
PC breakpoint register
Data breakpoint register
Data breakpoint mask register
Data breakpoint 1 register
Data breakpoint mask 1 register
Trigger definition register
Extended trigger definition register
XTDR
Configuration/status register
BDM address attributes register
PC breakpoint 2 register
Note: Each debug register is accessed as a 32-bit register; shaded fields above are not used (don’t care).
All debug control registers are writable from the external development system or the CPU via the WDEBUG
instruction.
CSR is write-only from the programming model. It can be read from and written to through the BDM port.
CSR is accessible in supervisor mode as debug control register 0x00 using the WDEBUG instruction and
Address attribute trigger register
Address low breakpoint register
Address high breakpoint register
Address 1 attribute trigger register
Address low breakpoint 1 register
Address high breakpoint 1 register
31
15
7
0
31
15
7
0
31
15
7
0
31
15
0
31
15
0
31
15
0
31
15
0
31
15
31
15
0
31
15
0
31
15
0
31
15
0
31
15
0
31
15
0
AATR
ABLR
ABHR
BAAR
CSR
DBR
DBMR
PBR
DBR1
DBMR1
PBR1
PBR2
PBR3
PBMR
TDR