Freescale Semiconductor MCF5480 - Manual (Page 265)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 8-15
qualification. Reset clears these fields, disabling qualifications and defaulting to the Revision C debug
module functionality.
8.4.4 BDM Address Attribute Register (BAAR)
The BAAR defines the address space for memory-referencing BDM commands. To maintain
compatibility with Revision A, BAAR is loaded with any data written to the LSB of AATR. See
Figure 8-8 . The reset value of 0x5 sets supervisor data as the default address space.
BAAR is write only. BAAR[R,SZ] are loaded directly from the BDM command. BAAR[TT,TM] can be
programmed as debug control register 0x05 from the external development system. For compatibility with
Rev. A, BAAR is loaded each time AATR is written.
Table 8-10 describes BAAR fields.
Table 8-9. PBAC Field Descriptions
Bits Name Description
31-16 — Reserved, should be cleared.
15–12 PBR3AC PBRn ASID control. Corresponds to the ASID control associated with PBRn. Determines
whether the ASID is included in the PC breakpoint comparison and whether the operating
mode (supervisor or user) is included in the comparison logic.
x00x No ASID qualification; no mode qualification
x010 No ASID qualification; user mode qualification enabled
x011 No ASID qualification; supervisor mode qualification enabled
x10x ASID qualification enabled; no mode qualification
x110 ASID qualification enabled; user mode qualification enabled
x111 ASID qualification enabled; supervisor mode qualification enabled
11–8 PBR2AC
7–4 PBR1AC
3–0 PBRAC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0 R SZ TT TM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Reg
Addr
CPU + 0x05
Figure 8-8. BDM Address Attribute Register (BAAR)
Table 8-10. BAAR Field Descriptions
Bits Name Description
31-8 — Reserved
7 R Read/write
0 Write
1 Read