11 extended trigger definition register (xtdr), Extended trigger definition register (xtdr) -25 – Freescale Semiconductor MCF5480 User Manual
Page 275
Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
8-25
8.4.11
Extended Trigger Definition Register (XTDR)
The XTDR configures the operation of the hardware breakpoint logic that corresponds with the
ABHR1/ABLR1/AATR1 and DBR1/DBMR1 registers within the debug module and, in conjunction with
the TDR and its associated debug registers, controls the actions taken under the defined conditions. The
breakpoint logic may be configured as a one- or two-level trigger, where TDR[31–16] or XTDR[31–16]
define the second-level trigger and bits 15–0 define the first-level trigger. The XTDR is accessible in
supervisor mode as debug control register 0x17 using the WDEBUG instruction and via the BDM port
using the
WDMREG
command.
NOTE
The debug module has no hardware interlocks, so to prevent spurious
breakpoint triggers while the breakpoint registers are being loaded, disable
TDR and XTDR (by clearing TDR[29,13] and XTDR[29,13]) before
defining triggers.
A write to the XTDR clears the trigger status bits, CSR[BSTAT].
When cleared, the data enable bits (EDxx) for both the second level and first level triggers disable data
breakpoints. When set, these bits enable the corresponding data breakpoint condition based on the size and
placement on the processor’s local data bus.
The address breakpoint for each trigger is enabled by setting the address enable bits (EAx); clearing all
three bits disables the corresponding breakpoint.
Section 8.4.11.1, “Resulting Set of Possible Trigger Combinations
,” describes how to handle multiple
breakpoint conditions.
15–8
PBA1SID PBR1ASID.
Corresponds
to the ASID associated with PBR1.
7–0
PBASID
PBRASID. Corresponds to the ASID associated with PBR.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Second Level Triggers
R
0
0
EBL
2
EDLW
2
EDWL
2
EDWU
2
EDLL
2
EDLM
2
EDUM
2
EDUU
2
DI
2
EAI
2
EAR
2
EAL
2
0
0
W
—
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
First Level Triggers
R
0
0
EBL
1
EDLW
1
EDWL
1
EDWU
1
EDLL
1
EDLM
1
EDUM
1
EDUU
1
DI
1
EAI
1
EAR
1
EAL
1
0
0
W
—
—
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
CPU + 0x17
Figure 8-17. Extended Trigger Definition Register (XTDR)
Table 8-20. PBASID Field Descriptions (Continued)
Bits
Name
Description