11 read control register (rcreg) – Freescale Semiconductor MCF5480 User Manual
Page 295
Background Debug Mode (BDM)
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
8-45
Figure 8-42.
FORCE
_
TA
Command Sequence
Operand Data:
None
Result Data:
The command complete response, 0xFFFF (with the status bit cleared), is returned
during the next shift operation. This response indicates the
FORCE
_
TA
command
was processed correctly and does not necessarily reflect the status of any internal
bus.
8.5.3.3.11
Read Control Register (
RCREG
)
Read the selected control register and return the 32-bit result. Accesses to the processor/memory control
registers are always 32 bits wide, regardless of register width. The second and third words of the command
form a 32-bit address, which the debug module uses to generate a special bus cycle to access the specified
control register. The 12-bit Rc field is the same as that used by the MOVEC instruction.
Command/Result Formats:
Command Sequence:
Figure 8-44.
RCREG
Command Sequence
Operand Data:
The only operand is the 32-bit Rc control register select field.
Result Data:
Control register contents are returned as a longword, most-significant word first.
The implemented portion of registers smaller than 32 bits is guaranteed correct;
other bits are undefined.
Rc encoding: See
15
12
11
8
7
4
3
0
Command
0x2
0x9
0x8
0x0
0x0
0x0
0x0
0x0
0x0
Rc
Result
D[31:16]
D[15:0]
Figure 8-43.
RCREG
Command/Result Formats
FORCE_TA
???
NEXT CMD
“CMD COMPLETE”
XXX
’NOT READY’
RCREG
???
MS ADDR
’NOT READY’
MS ADDR
’NOT READY’
NEXT CMD
’NOT READY’
READ
CONTROL
REGISTER
XXX
BERR
NEXT CMD
MS RESULT
NEXT CMD
LS RESULT