Freescale Semiconductor MCF5480 - Manual (Page 298)

MCF548x Reference Manual, Rev. 3
8-48 Freescale Semiconductor
Likewise, to write an accumulator register, the following BDM sequence is needed:
BdmWriteACCx (
rcreg macsr; // read current macsr contents & save
wcreg #0,macsr; // disable all rounding modes
wcreg #data,ACCx; // write the desired accumulator
wcreg #saved_data,macsr; // restore the original macsr
)
Additionally, writes to the accumulator extension registers must be performed after the corresponding
accumulators are updated because a write to any accumulator alters the corresponding extension register
contents.
For more information on saving and restoring the complete EMAC programming model, see the
appropriate section of the EMAC chapter.
8.5.3.3.14 BDM Accesses of Floating-Point Data Registers (FPn)
The ColdFire debug architecture allows BDM accesses of the entire programming model (including all
FPU-related registers) of the processor core using RCREG and WCREG . However, certain hardware
restrictions require the accesses related to the 64-bit FPn data registers be performed in a certain manner
to guarantee correct operation.
The serial BDM command structure supports 8-, 16- and 32-bit accesses, but there is no direct mechanism
for accessing 64-bit data values. Rather than changing this well-established protocol and command set,
BDM accesses of 64-bit data values are treated as two independent 32-bit references. In particular, 64-bit
FPn data registers are treated as two separate values from the BDM perspective. Each FPn is partitioned
into upper and lower longwords, FPUn and FPLn.
Either longword can be read first. The processor treats the BDM read command as a pseudo-FMOVEM.
Accordingly, all rounding modes and exception enables are ignored and the 32-bit contents of FPUn or
FPLn are sent to the debug module for transmission over the serial communication channel. The FPU
programming model is unchanged.
To write to an FPU data register, FPUn must be written first and followed by a write to FPLn. The
processor operates as follows: the BDM write to FPUn is performed, which loads the upper 32 bits of an
internal double-precision operand register; the BDM write to FPLn loads the supplied operand into the
lower 32 bits of the same internal register, and the entire 64-bit value is loaded into the selected FPn.
Failure to execute this sequence of commands produces an undefined value in the FPUn.
Note that any BDM write of an FPU register changes the internal state from NULL to IDLE.
8.5.3.3.15 Write Control Register ( WCREG )
The operand (longword) data is written to the specified control register. The write alters all 32 register bits.
See the RCREG instruction description for the Rc encoding and for additional notes on writes to the A7
stack pointers and the EMAC and FPU programming models.
Command/Result Formats: