Freescale Semiconductor MCF5480 - Manual (Page 313)

Freescale-Recommended BDM Pinout
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 8-63
Additionally, the execution of the debug interrupt service routine is forced to be interrupt-inhibited by the
processor hardware. While in this service routine, there is an optional capability to map all instruction and
operand references into a separate address space, so that an emulator could define the routine dynamically.
The current processor implementations actually include a program-invisible state bit that defines this
emulator mode of operation. Also note, the interrupt mask level is not modified during the processing of
a debug interrupt.
Customers with real-time embedded systems have specifically asked for the ability to service normal
interrupt requests while processing the debug interrupt service routine. In many systems of this type,
motion-based servo interrupts must be considered as the highest priority interrupt request.
To provide this functionality and be able to service any number of normal interrupt requests (including the
possibility of nested interrupts), the processor state signaling emulator mode must be included as part of
the exception stack frame.
As part of the Rev. C functionality, the operation of the debug interrupt is modified in the following
manner:
1. The occurrence of the breakpoint trigger, configured to generate a debug interrupt, is treated
exactly as before. The debug interrupt is treated as a higher priority exception relative to the normal
interrupt requests encoded on the interrupt priority input signals.
2. At the appropriate sample point, the ColdFire processor initiates debug interrupt exception
processing. This event is signaled externally by the generation of a unique PST value (PST =
0xD) asserted for multiple cycles. The processor sets the emulator mode state bit as part of this
exception processing.
3. While the processor in the debug interrupt service routine, all normal interrupt requests are
evaluated and sampled once per instruction. While in this routine, if any type of exception occurs,
the processor responds in the following manner:
a) In response to the new exception, the processor saves a copy of the current value of the
emulator mode state bit and then exits emulator mode by clearing the actual state.
b) The new exception stack frame sets bit 1 of the fault status field, using the saved emulator
mode bit, indicating execution while in emulator mode has been interrupted. This corresponds
to bit 17 of the longword at the top of the system stack.
c) Control is passed to the appropriate exception handler.
d) When the exception handler is complete, a Return From Exception (RTE) instruction is
executed. During the processing of the RTE, FS[1] is reloaded from the system stack. If this
bit is asserted, the processor sets the emulator mode state and resumes execution of the
original debug interrupt service routine. This is signaled externally by the generation of the
PST value that originally identified the occurrence of a debug interrupt exception, that is,
PST = 0xD.
Implementation of this revised debug interrupt handling fully supports the servicing of any number of
normal interrupt requests while in a debug interrupt service routine. The emulator mode state bit is
essentially changed to be a program-visible value, stored into memory during exception stack frame
creation and loaded from memory by the RTE instruction.
8.9 Freescale-Recommended BDM Pinout
The ColdFire BDM connector, Figure 8-51 , is a 26-pin Berg connector arranged 2 x 13.