Freescale Semiconductor MCF5480 - Manual (Page 332)

MCF548x Reference Manual, Rev. 3
10-10 Freescale Semiconductor
10.3.3.2 Arbiter Version Register (XARB_VER)
4 — Reserved, should be cleared.
3 BA Bus Activity Time-out Enable. If enabled, the arbiter will set the Bus Activity Time-out Status bit
(XARB_SR[BA]) when the Bus Activity Time-out is reached. Bus Activity Time-out is derived from
the arbiter bus activity time out count register.
0 Disable bus activity time-out
1 Enable bus activity time-out
2 DT Data Tenure Time-out Enable. If enabled, the arbiter will transfer error acknowledge when the Data
Tenure Time-out is reached. Data Tenure Time-out is derived from the arbiter data tenure time out
count register. Also, the arbiter will set the Data Tenure Time-out Status bit (Arbiter Status Register
Bit 30). Setting this bit will also enable the Address Tenure Time-out. This is required to ensure that
a data time-out will not occur before an address acknowledge.
0 Disable data tenure time-out
1 Enable data tenure time-out
1 AT Address Tenure Time-out Enable. If enabled, the arbiter will AACK and TEA (if required) when the
Address Tenure Time-out is reached. Address Tenure Time-out is derived from the Arbiter Address
Tenure Time Out Count register. Also, the arbiter will set the Address Tenure Time-out Status bit
(Arbiter Status Register Bit 31). Address Tenure Time-out is also enabled by the DT bit above.
0 Disable address tenure time-out
1 Enable address tenure time-out
0 — Reserved, should be cleared.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R VER
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VER
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Reg
Addr
MBAR + 0x0244
Figure 10-6. Arbiter Version Register (XARB_VER)
Table 10-6. VER Field Descriptions
Bit Name Description
31–0 VER Hardware Version ID. The current version number is 0x0001.
Table 10-5. XARB_CFG Bit Descriptions (Continued)
Bit Name Description