5 arbiter address capture register (xarb_adrcap), Arbiter address capture register (xarb_adrcap) -13 – Freescale Semiconductor MCF5480 User Manual
Page 335
XL Bus Arbiter
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
10-13
10.3.3.5
Arbiter Address Capture Register (XARB_ADRCAP)
The arbiter address capture register will capture the address for a tenure that has an address time-out, data
time-out, or there is a transfer error acknowledge from another source. This value is held until unlocked
by writing any value to the arbiter address capture register or arbiter bus signal capture register. This value
is also unlocked by writing a 1 to either XARB_SR[DT] or XARB_SR[AT]. Unlocking the register does
not clear its contents.
10.3.3.6
Arbiter Bus Signal Capture Register (XARB_SIGCAP)
Important bus signals are captured when a bus error occurs. This happens on an address time-out, data
time-out, or any transfer error acknowledge.
The arbiter bus signal capture register will capture TT, TBST, and TSIZ for a tenure that has an address
time-out or data time-out, or there is a transfer error acknowledge from another source. These values are
held until unlocked by writing any value to the arbiter address capture register (XARB_ADRCAP) or
arbiter bus signal capture register (XARB_SIGCAP). These values are also unlocked by writing a 1 to
either XARB_SR[DT] or XARB_SR[AT]. Unlocking the register does not clear its contents.
1
DTE
Data Tenure Time-out interrupt enable.
0 The corresponding interrupt source is masked.
1 The corresponding interrupt source is enabled.
0
ATE
Address Tenure Time-out interrupt enable.
0 The corresponding interrupt source is masked.
1 The corresponding interrupt source is enabled.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
ADRCAP
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
ADRCAP
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x0250
Figure 10-9. Arbiter Address Capture Register (XARB_ADRCAP)
Table 10-9. XARB_ADRCAP Field Descriptions
Bits
Name
Description
31–0
ADRCAP
Address that is captured when a bus error occurs. This happens on an address time-out,
data time-out, or any transfer error acknowledge.
Table 10-8. XARB_IMR Field Descriptions (Continued)
Bits
Name
Description