Freescale Semiconductor MCF5480 - Manual (Page 338)

MCF548x Reference Manual, Rev. 3
10-16 Freescale Semiconductor
10.3.3.9 Arbiter Bus Activity Time Out Register (XARB_BUSTO)
10.3.3.10 Arbiter Master Priority Enable Register (XARB_PRIEN)
The arbiter master priority enable register determines whether the arbiter uses the hardwired or software
programmable priority for a master. The default is enabled for all masters. Both methods may be used at
the same time for different masters. This register may be written at any time. The change will become
effective 1 clock after the register is written.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R BUSTO
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BUSTO
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Reg
Addr
MBAR + 0x0260
Figure 10-13. Arbiter Bus Activity Time Out Register (XARB_BUSTO)
Table 10-13. XARB_BUSTO Field Descriptions
Bits Name Description
31–0 BUSTO Bus activity time-out counter value in XLB clocks.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0 — — — — M3 M2 — M0
W
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Reg
Addr
MBAR + 0x0264
Figure 10-14. Arbiter Master Priority Enable Register (XARB_PRIEN)